Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright 2018 Mellanox Technologies, Ltd
3 : : */
4 : :
5 : : #include <unistd.h>
6 : :
7 : : #include <eal_export.h>
8 : : #include <rte_errno.h>
9 : : #include <rte_malloc.h>
10 : : #include <rte_eal_paging.h>
11 : :
12 : : #include "mlx5_prm.h"
13 : : #include "mlx5_devx_cmds.h"
14 : : #include "mlx5_common_log.h"
15 : : #include "mlx5_malloc.h"
16 : :
17 : : /* FW writes status value to the OUT buffer at offset 00H */
18 : : #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status)
19 : : /* FW writes syndrome value to the OUT buffer at offset 04H */
20 : : #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome)
21 : :
22 : : #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1))
23 : :
24 : : #define DEVX_DRV_LOG(level, out, reason, param, value) \
25 : : do { \
26 : : /* \
27 : : * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \
28 : : * do not expand correctly when the macro invoked when the `param` \
29 : : * is `NULL`. \
30 : : * Use `local_param` to avoid direct `NULL` expansion. \
31 : : */ \
32 : : const char *local_param = (const char *)param; \
33 : : \
34 : : rte_errno = errno; \
35 : : if (!local_param) { \
36 : : DRV_LOG(level, \
37 : : "DevX %s failed errno=%d status=%#x syndrome=%#x", \
38 : : (reason), errno, MLX5_FW_STATUS((out)), \
39 : : MLX5_FW_SYNDROME((out))); \
40 : : } else { \
41 : : DRV_LOG(level, \
42 : : "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\
43 : : (reason), local_param, (value), errno, \
44 : : MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \
45 : : } \
46 : : } while (0)
47 : :
48 : : static void *
49 [ # # ]: 0 : mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out,
50 : : int *err, uint32_t flags)
51 : : {
52 : : const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int);
53 : : const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int);
54 : : int rc;
55 : :
56 : : memset(in, 0, size_in);
57 : : memset(out, 0, size_out);
58 [ # # ]: 0 : MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
59 [ # # ]: 0 : MLX5_SET(query_hca_cap_in, in, op_mod, flags);
60 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out);
61 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
62 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1);
63 [ # # ]: 0 : if (err)
64 [ # # ]: 0 : *err = MLX5_DEVX_ERR_RC(rc);
65 : 0 : return NULL;
66 : : }
67 [ # # ]: 0 : if (err)
68 : 0 : *err = 0;
69 : 0 : return MLX5_ADDR_OF(query_hca_cap_out, out, capability);
70 : : }
71 : :
72 : : /**
73 : : * Perform read access to the registers. Reads data from register
74 : : * and writes ones to the specified buffer.
75 : : *
76 : : * @param[in] ctx
77 : : * Context returned from mlx5 open_device() glue function.
78 : : * @param[in] reg_id
79 : : * Register identifier according to the PRM.
80 : : * @param[in] arg
81 : : * Register access auxiliary parameter according to the PRM.
82 : : * @param[out] data
83 : : * Pointer to the buffer to store read data.
84 : : * @param[in] dw_cnt
85 : : * Buffer size in double words.
86 : : *
87 : : * @return
88 : : * 0 on success, a negative value otherwise.
89 : : */
90 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_register_read)
91 : : int
92 : 0 : mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
93 : : uint32_t *data, uint32_t dw_cnt)
94 : : {
95 : 0 : uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0};
96 : 0 : uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
97 : : MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
98 : : int rc;
99 : :
100 : : MLX5_ASSERT(data && dw_cnt);
101 : : MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
102 [ # # ]: 0 : if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
103 : 0 : DRV_LOG(ERR, "Not enough buffer for register read data");
104 : 0 : return -1;
105 : : }
106 : 0 : MLX5_SET(access_register_in, in, opcode,
107 : : MLX5_CMD_OP_ACCESS_REGISTER_USER);
108 : 0 : MLX5_SET(access_register_in, in, op_mod,
109 : : MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
110 : 0 : MLX5_SET(access_register_in, in, register_id, reg_id);
111 : 0 : MLX5_SET(access_register_in, in, argument, arg);
112 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
113 : 0 : MLX5_ST_SZ_BYTES(access_register_out) +
114 : : sizeof(uint32_t) * dw_cnt);
115 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
116 [ # # # # ]: 0 : DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id);
117 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
118 : : }
119 : 0 : memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
120 : : dw_cnt * sizeof(uint32_t));
121 : 0 : return 0;
122 : : }
123 : :
124 : : /**
125 : : * Perform write access to the registers.
126 : : *
127 : : * @param[in] ctx
128 : : * Context returned from mlx5 open_device() glue function.
129 : : * @param[in] reg_id
130 : : * Register identifier according to the PRM.
131 : : * @param[in] arg
132 : : * Register access auxiliary parameter according to the PRM.
133 : : * @param[out] data
134 : : * Pointer to the buffer containing data to write.
135 : : * @param[in] dw_cnt
136 : : * Buffer size in double words (32bit units).
137 : : *
138 : : * @return
139 : : * 0 on success, a negative value otherwise.
140 : : */
141 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_register_write)
142 : : int
143 : 0 : mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg,
144 : : uint32_t *data, uint32_t dw_cnt)
145 : : {
146 : 0 : uint32_t in[MLX5_ST_SZ_DW(access_register_in) +
147 : : MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
148 : 0 : uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0};
149 : : int rc;
150 : : void *ptr;
151 : :
152 : : MLX5_ASSERT(data && dw_cnt);
153 : : MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
154 [ # # ]: 0 : if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
155 : 0 : DRV_LOG(ERR, "Data to write exceeds max size");
156 : 0 : return -1;
157 : : }
158 : 0 : MLX5_SET(access_register_in, in, opcode,
159 : : MLX5_CMD_OP_ACCESS_REGISTER_USER);
160 : 0 : MLX5_SET(access_register_in, in, op_mod,
161 : : MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE);
162 : 0 : MLX5_SET(access_register_in, in, register_id, reg_id);
163 : 0 : MLX5_SET(access_register_in, in, argument, arg);
164 : : ptr = MLX5_ADDR_OF(access_register_in, in, register_data);
165 : 0 : memcpy(ptr, data, dw_cnt * sizeof(uint32_t));
166 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
167 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
168 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id);
169 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
170 : : }
171 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in,
172 : 0 : MLX5_ST_SZ_BYTES(access_register_in) +
173 : : dw_cnt * sizeof(uint32_t),
174 : : out, sizeof(out));
175 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
176 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id);
177 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
178 : : }
179 : : return 0;
180 : : }
181 : :
182 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_counter_alloc_general)
183 : : struct mlx5_devx_obj *
184 : 0 : mlx5_devx_cmd_flow_counter_alloc_general(void *ctx,
185 : : struct mlx5_devx_counter_attr *attr)
186 : : {
187 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
188 : : 0, SOCKET_ID_ANY);
189 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
190 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
191 : :
192 [ # # ]: 0 : if (!dcs) {
193 : 0 : rte_errno = ENOMEM;
194 : 0 : return NULL;
195 : : }
196 : 0 : MLX5_SET(alloc_flow_counter_in, in, opcode,
197 : : MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
198 [ # # ]: 0 : if (attr->bulk_log_max_alloc)
199 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk_log_size,
200 : : attr->flow_counter_bulk_log_size);
201 : : else
202 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk,
203 : : attr->bulk_n_128);
204 [ # # ]: 0 : if (attr->pd_valid)
205 : 0 : MLX5_SET(alloc_flow_counter_in, in, pd, attr->pd);
206 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
207 : : sizeof(in), out, sizeof(out));
208 [ # # ]: 0 : if (!dcs->obj) {
209 : 0 : DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
210 : 0 : rte_errno = errno;
211 : 0 : mlx5_free(dcs);
212 : 0 : return NULL;
213 : : }
214 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
215 : 0 : return dcs;
216 : : }
217 : :
218 : : /**
219 : : * Allocate flow counters via devx interface.
220 : : *
221 : : * @param[in] ctx
222 : : * Context returned from mlx5 open_device() glue function.
223 : : * @param dcs
224 : : * Pointer to counters properties structure to be filled by the routine.
225 : : * @param bulk_n_128
226 : : * Bulk counter numbers in 128 counters units.
227 : : *
228 : : * @return
229 : : * Pointer to counter object on success, a negative value otherwise and
230 : : * rte_errno is set.
231 : : */
232 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_counter_alloc)
233 : : struct mlx5_devx_obj *
234 : 0 : mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
235 : : {
236 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
237 : : 0, SOCKET_ID_ANY);
238 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
239 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
240 : :
241 [ # # ]: 0 : if (!dcs) {
242 : 0 : rte_errno = ENOMEM;
243 : 0 : return NULL;
244 : : }
245 : 0 : MLX5_SET(alloc_flow_counter_in, in, opcode,
246 : : MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
247 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
248 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
249 : : sizeof(in), out, sizeof(out));
250 [ # # ]: 0 : if (!dcs->obj) {
251 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0);
252 : 0 : mlx5_free(dcs);
253 : 0 : return NULL;
254 : : }
255 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
256 : 0 : return dcs;
257 : : }
258 : :
259 : : /**
260 : : * Query flow counters values.
261 : : *
262 : : * @param[in] dcs
263 : : * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
264 : : * @param[in] clear
265 : : * Whether hardware should clear the counters after the query or not.
266 : : * @param[in] n_counters
267 : : * 0 in case of 1 counter to read, otherwise the counter number to read.
268 : : * @param pkts
269 : : * The number of packets that matched the flow.
270 : : * @param bytes
271 : : * The number of bytes that matched the flow.
272 : : * @param mkey
273 : : * The mkey key for batch query.
274 : : * @param addr
275 : : * The address in the mkey range for batch query.
276 : : * @param cmd_comp
277 : : * The completion object for asynchronous batch query.
278 : : * @param async_id
279 : : * The ID to be returned in the asynchronous batch query response.
280 : : *
281 : : * @return
282 : : * 0 on success, a negative value otherwise.
283 : : */
284 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_counter_query)
285 : : int
286 : 0 : mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
287 : : int clear, uint32_t n_counters,
288 : : uint64_t *pkts, uint64_t *bytes,
289 : : uint32_t mkey, void *addr,
290 : : void *cmd_comp,
291 : : uint64_t async_id)
292 : : {
293 : : uint32_t out[MLX5_ST_SZ_BYTES(query_flow_counter_out) + MLX5_ST_SZ_BYTES(traffic_counter)];
294 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
295 : : const int out_len = RTE_DIM(out);
296 : : void *stats;
297 : : int rc;
298 : :
299 : 0 : MLX5_SET(query_flow_counter_in, in, opcode,
300 : : MLX5_CMD_OP_QUERY_FLOW_COUNTER);
301 : 0 : MLX5_SET(query_flow_counter_in, in, op_mod, 0);
302 : 0 : MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
303 : 0 : MLX5_SET(query_flow_counter_in, in, clear, !!clear);
304 : :
305 [ # # ]: 0 : if (n_counters) {
306 [ # # ]: 0 : MLX5_SET(query_flow_counter_in, in, num_of_counters,
307 : : n_counters);
308 [ # # ]: 0 : MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
309 : 0 : MLX5_SET(query_flow_counter_in, in, mkey, mkey);
310 : 0 : MLX5_SET64(query_flow_counter_in, in, address,
311 : : (uint64_t)(uintptr_t)addr);
312 : : }
313 [ # # ]: 0 : if (!cmd_comp)
314 : 0 : rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
315 : : out_len);
316 : : else
317 : 0 : rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
318 : : out_len, async_id,
319 : : cmd_comp);
320 [ # # ]: 0 : if (rc) {
321 : 0 : DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
322 : 0 : rte_errno = rc;
323 : 0 : return -rc;
324 : : }
325 [ # # ]: 0 : if (!n_counters) {
326 : : stats = MLX5_ADDR_OF(query_flow_counter_out,
327 : : out, flow_statistics);
328 [ # # ]: 0 : *pkts = MLX5_GET64(traffic_counter, stats, packets);
329 [ # # ]: 0 : *bytes = MLX5_GET64(traffic_counter, stats, octets);
330 : : }
331 : : return 0;
332 : : }
333 : :
334 : : /**
335 : : * Create a new mkey.
336 : : *
337 : : * @param[in] ctx
338 : : * Context returned from mlx5 open_device() glue function.
339 : : * @param[in] attr
340 : : * Attributes of the requested mkey.
341 : : *
342 : : * @return
343 : : * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
344 : : * is set.
345 : : */
346 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_mkey_create)
347 : : struct mlx5_devx_obj *
348 : 0 : mlx5_devx_cmd_mkey_create(void *ctx,
349 : : struct mlx5_devx_mkey_attr *attr)
350 : : {
351 : 0 : struct mlx5_klm *klm_array = attr->klm_array;
352 : 0 : int klm_num = attr->klm_num;
353 [ # # ]: 0 : int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
354 : 0 : (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
355 : 0 : uint32_t *in = alloca(sizeof(uint32_t) * in_size_dw);
356 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
357 : : void *mkc;
358 : 0 : struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
359 : : 0, SOCKET_ID_ANY);
360 : : size_t pgsize;
361 : : uint32_t translation_size;
362 : :
363 [ # # ]: 0 : if (!mkey) {
364 : 0 : rte_errno = ENOMEM;
365 : 0 : return NULL;
366 : : }
367 : : memset(in, 0, in_size_dw * 4);
368 : 0 : pgsize = rte_mem_page_size();
369 [ # # ]: 0 : if (pgsize == (size_t)-1) {
370 : 0 : mlx5_free(mkey);
371 : 0 : DRV_LOG(ERR, "Failed to get page size");
372 : 0 : rte_errno = ENOMEM;
373 : 0 : return NULL;
374 : : }
375 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
376 : : mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
377 [ # # ]: 0 : if (klm_num > 0) {
378 : : int i;
379 : 0 : uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
380 : : klm_pas_mtt);
381 : 0 : translation_size = RTE_ALIGN(klm_num, 4);
382 [ # # ]: 0 : for (i = 0; i < klm_num; i++) {
383 [ # # ]: 0 : MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
384 [ # # ]: 0 : MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
385 [ # # ]: 0 : MLX5_SET64(klm, klm, address, klm_array[i].address);
386 : 0 : klm += MLX5_ST_SZ_BYTES(klm);
387 : : }
388 [ # # ]: 0 : for (; i < (int)translation_size; i++) {
389 [ # # ]: 0 : MLX5_SET(klm, klm, mkey, 0x0);
390 : 0 : MLX5_SET64(klm, klm, address, 0x0);
391 : 0 : klm += MLX5_ST_SZ_BYTES(klm);
392 : : }
393 [ # # # # ]: 0 : MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
394 : : MLX5_MKC_ACCESS_MODE_KLM_FBS :
395 : : MLX5_MKC_ACCESS_MODE_KLM);
396 [ # # ]: 0 : MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
397 : : } else {
398 : 0 : translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
399 [ # # ]: 0 : MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
400 [ # # # # ]: 0 : MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
401 : : }
402 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
403 : : translation_size);
404 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
405 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
406 [ # # ]: 0 : MLX5_SET(mkc, mkc, lw, 0x1);
407 [ # # ]: 0 : MLX5_SET(mkc, mkc, lr, 0x1);
408 [ # # ]: 0 : if (attr->set_remote_rw) {
409 [ # # ]: 0 : MLX5_SET(mkc, mkc, rw, 0x1);
410 [ # # ]: 0 : MLX5_SET(mkc, mkc, rr, 0x1);
411 : : }
412 [ # # ]: 0 : MLX5_SET(mkc, mkc, qpn, 0xffffff);
413 [ # # ]: 0 : MLX5_SET(mkc, mkc, pd, attr->pd);
414 [ # # ]: 0 : MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
415 [ # # ]: 0 : MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
416 [ # # ]: 0 : MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
417 [ # # ]: 0 : MLX5_SET(mkc, mkc, relaxed_ordering_write,
418 : : attr->relaxed_ordering_write);
419 [ # # ]: 0 : MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
420 [ # # ]: 0 : MLX5_SET64(mkc, mkc, start_addr, attr->addr);
421 [ # # ]: 0 : MLX5_SET64(mkc, mkc, len, attr->size);
422 [ # # ]: 0 : MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en);
423 [ # # ]: 0 : if (attr->crypto_en) {
424 [ # # ]: 0 : MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en);
425 [ # # ]: 0 : MLX5_SET(mkc, mkc, bsf_octword_size, 4);
426 : : }
427 : 0 : mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
428 : : sizeof(out));
429 [ # # ]: 0 : if (!mkey->obj) {
430 [ # # # # : 0 : DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey"
# # ]
431 : : : "create direct key", NULL, 0);
432 : 0 : mlx5_free(mkey);
433 : 0 : return NULL;
434 : : }
435 [ # # ]: 0 : mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
436 : 0 : mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
437 : 0 : return mkey;
438 : : }
439 : :
440 : : /**
441 : : * Get status of devx command response.
442 : : * Mainly used for asynchronous commands.
443 : : *
444 : : * @param[in] out
445 : : * The out response buffer.
446 : : *
447 : : * @return
448 : : * 0 on success, non-zero value otherwise.
449 : : */
450 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_get_out_command_status)
451 : : int
452 : 0 : mlx5_devx_get_out_command_status(void *out)
453 : : {
454 : : int status;
455 : :
456 [ # # ]: 0 : if (!out)
457 : : return -EINVAL;
458 [ # # ]: 0 : status = MLX5_GET(query_flow_counter_out, out, status);
459 [ # # ]: 0 : if (status) {
460 [ # # ]: 0 : int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
461 : :
462 : 0 : DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
463 : : syndrome);
464 : : }
465 : : return status;
466 : : }
467 : :
468 : : /**
469 : : * Destroy any object allocated by a Devx API.
470 : : *
471 : : * @param[in] obj
472 : : * Pointer to a general object.
473 : : *
474 : : * @return
475 : : * 0 on success, a negative value otherwise.
476 : : */
477 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_destroy)
478 : : int
479 : 0 : mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
480 : : {
481 : : int ret;
482 : :
483 [ # # ]: 0 : if (!obj)
484 : : return 0;
485 : 0 : ret = mlx5_glue->devx_obj_destroy(obj->obj);
486 : 0 : mlx5_free(obj);
487 : 0 : return ret;
488 : : }
489 : :
490 : : /**
491 : : * Query NIC vport context.
492 : : * Fills minimal inline attribute.
493 : : *
494 : : * @param[in] ctx
495 : : * ibv contexts returned from mlx5dv_open_device.
496 : : * @param[in] vport
497 : : * vport index
498 : : * @param[out] attr
499 : : * Attributes device values.
500 : : *
501 : : * @return
502 : : * 0 on success, a negative value otherwise.
503 : : */
504 : : static int
505 : 0 : mlx5_devx_cmd_query_nic_vport_context(void *ctx,
506 : : unsigned int vport,
507 : : struct mlx5_hca_attr *attr)
508 : : {
509 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
510 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
511 : : void *vctx;
512 : : int rc;
513 : :
514 : : /* Query NIC vport context to determine inline mode. */
515 : 0 : MLX5_SET(query_nic_vport_context_in, in, opcode,
516 : : MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
517 : 0 : MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
518 [ # # ]: 0 : if (vport)
519 [ # # ]: 0 : MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
520 : 0 : rc = mlx5_glue->devx_general_cmd(ctx,
521 : : in, sizeof(in),
522 : : out, sizeof(out));
523 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
524 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0);
525 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
526 : : }
527 : : vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
528 : : nic_vport_context);
529 [ # # ]: 0 : if (attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
530 [ # # ]: 0 : attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
531 : : min_wqe_inline_mode);
532 [ # # ]: 0 : attr->system_image_guid = MLX5_GET64(nic_vport_context, vctx,
533 : : system_image_guid);
534 : 0 : return 0;
535 : : }
536 : :
537 : : /**
538 : : * Query NIC vDPA attributes.
539 : : *
540 : : * @param[in] ctx
541 : : * Context returned from mlx5 open_device() glue function.
542 : : * @param[out] vdpa_attr
543 : : * vDPA Attributes structure to fill.
544 : : */
545 : : static void
546 : 0 : mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
547 : : struct mlx5_hca_vdpa_attr *vdpa_attr)
548 : : {
549 : : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
550 : : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
551 : : void *hcattr;
552 : :
553 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL,
554 : : MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
555 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
556 [ # # ]: 0 : if (!hcattr) {
557 : 0 : DRV_LOG(DEBUG, "Failed to query devx VDPA capabilities");
558 : 0 : vdpa_attr->valid = 0;
559 : : } else {
560 : 0 : vdpa_attr->valid = 1;
561 : 0 : vdpa_attr->desc_tunnel_offload_type =
562 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
563 : : desc_tunnel_offload_type);
564 : 0 : vdpa_attr->eth_frame_offload_type =
565 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
566 : : eth_frame_offload_type);
567 : 0 : vdpa_attr->virtio_version_1_0 =
568 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
569 : : virtio_version_1_0);
570 [ # # ]: 0 : vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
571 : : tso_ipv4);
572 [ # # ]: 0 : vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
573 : : tso_ipv6);
574 [ # # ]: 0 : vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
575 : : tx_csum);
576 [ # # ]: 0 : vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
577 : : rx_csum);
578 [ # # ]: 0 : vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
579 : : event_mode);
580 : 0 : vdpa_attr->virtio_queue_type =
581 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
582 : : virtio_queue_type);
583 : 0 : vdpa_attr->log_doorbell_stride =
584 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
585 : : log_doorbell_stride);
586 : 0 : vdpa_attr->vnet_modify_ext =
587 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
588 : : vnet_modify_ext);
589 : 0 : vdpa_attr->virtio_net_q_addr_modify =
590 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
591 : : virtio_net_q_addr_modify);
592 : 0 : vdpa_attr->virtio_q_index_modify =
593 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
594 : : virtio_q_index_modify);
595 : 0 : vdpa_attr->log_doorbell_bar_size =
596 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
597 : : log_doorbell_bar_size);
598 : 0 : vdpa_attr->doorbell_bar_offset =
599 [ # # ]: 0 : MLX5_GET64(virtio_emulation_cap, hcattr,
600 : : doorbell_bar_offset);
601 : 0 : vdpa_attr->max_num_virtio_queues =
602 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
603 : : max_num_virtio_queues);
604 [ # # ]: 0 : vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
605 : : umem_1_buffer_param_a);
606 [ # # ]: 0 : vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
607 : : umem_1_buffer_param_b);
608 [ # # ]: 0 : vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
609 : : umem_2_buffer_param_a);
610 [ # # ]: 0 : vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
611 : : umem_2_buffer_param_b);
612 [ # # ]: 0 : vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
613 : : umem_3_buffer_param_a);
614 [ # # ]: 0 : vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
615 : : umem_3_buffer_param_b);
616 : : }
617 : 0 : }
618 : :
619 : : /**
620 : : * Query match sample handle parameters.
621 : : *
622 : : * This command allows translating a field sample handle returned by either
623 : : * PARSE_GRAPH_FLOW_MATCH_SAMPLE or by GENEVE TLV OPTION object into values
624 : : * used for header modification or header matching/hashing.
625 : : *
626 : : * @param[in] ctx
627 : : * Context used to create either GENEVE TLV option or FLEX PARSE GRAPH object.
628 : : * @param[in] sample_field_id
629 : : * Field sample handle returned by either PARSE_GRAPH_FLOW_MATCH_SAMPLE
630 : : * or by GENEVE TLV OPTION object.
631 : : * @param[out] attr
632 : : * Pointer to match sample info attributes structure.
633 : : *
634 : : * @return
635 : : * 0 on success, a negative errno otherwise and rte_errno is set.
636 : : */
637 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_match_sample_info_query)
638 : : int
639 : 0 : mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id,
640 : : struct mlx5_devx_match_sample_info_query_attr *attr)
641 : : {
642 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
643 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_match_sample_info_out)] = {0};
644 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_match_sample_info_in)] = {0};
645 : : int rc;
646 : :
647 : 0 : MLX5_SET(query_match_sample_info_in, in, opcode,
648 : : MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO);
649 : 0 : MLX5_SET(query_match_sample_info_in, in, op_mod, 0);
650 : 0 : MLX5_SET(query_match_sample_info_in, in, sample_field_id,
651 : : sample_field_id);
652 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
653 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
654 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "query match sample info",
655 : : "sample_field_id", sample_field_id);
656 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
657 : : }
658 [ # # ]: 0 : attr->modify_field_id = MLX5_GET(query_match_sample_info_out, out,
659 : : modify_field_id);
660 [ # # ]: 0 : attr->sample_dw_data = MLX5_GET(query_match_sample_info_out, out,
661 : : field_format_select_dw);
662 [ # # ]: 0 : attr->sample_dw_ok_bit = MLX5_GET(query_match_sample_info_out, out,
663 : : ok_bit_format_select_dw);
664 [ # # ]: 0 : attr->sample_dw_ok_bit_offset = MLX5_GET(query_match_sample_info_out,
665 : : out, ok_bit_offset);
666 : 0 : return 0;
667 : : #else
668 : : (void)ctx;
669 : : (void)sample_field_id;
670 : : (void)attr;
671 : : return -ENOTSUP;
672 : : #endif
673 : : }
674 : :
675 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_parse_samples)
676 : : int
677 : 0 : mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
678 : : uint32_t *ids,
679 : : uint32_t num, uint8_t *anchor)
680 : : {
681 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
682 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
683 : : void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
684 : : void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
685 : : void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
686 : : int ret;
687 : : uint32_t idx = 0;
688 : : uint32_t i;
689 : :
690 [ # # ]: 0 : if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
691 : 0 : rte_errno = EINVAL;
692 : 0 : DRV_LOG(ERR, "Too many sample IDs to be fetched.");
693 : 0 : return -rte_errno;
694 : : }
695 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
696 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
697 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
698 : : MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
699 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
700 : 0 : ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
701 : : out, sizeof(out));
702 [ # # ]: 0 : if (ret) {
703 : 0 : rte_errno = ret;
704 : 0 : DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
705 : : (void *)flex_obj);
706 : 0 : return -rte_errno;
707 : : }
708 [ # # ]: 0 : if (anchor)
709 [ # # ]: 0 : *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id);
710 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx < num; i++) {
711 : 0 : void *s_off = (void *)((char *)sample + i *
712 : : MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
713 : : uint32_t en;
714 : :
715 [ # # ]: 0 : en = MLX5_GET(parse_graph_flow_match_sample, s_off,
716 : : flow_match_sample_en);
717 [ # # ]: 0 : if (!en)
718 : 0 : continue;
719 [ # # ]: 0 : ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
720 : : flow_match_sample_field_id);
721 : : }
722 [ # # ]: 0 : if (num != idx) {
723 : 0 : rte_errno = EINVAL;
724 : 0 : DRV_LOG(ERR, "Number of sample IDs are not as expected.");
725 : 0 : return -rte_errno;
726 : : }
727 : : return ret;
728 : : }
729 : :
730 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_flex_parser)
731 : : struct mlx5_devx_obj *
732 : 0 : mlx5_devx_cmd_create_flex_parser(void *ctx,
733 : : struct mlx5_devx_graph_node_attr *data)
734 : : {
735 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
736 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
737 : : void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
738 : : void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
739 : : void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
740 : : void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
741 : : void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
742 : 0 : struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
743 : : (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
744 : : uint32_t i;
745 : :
746 [ # # ]: 0 : if (!parse_flex_obj) {
747 : 0 : DRV_LOG(ERR, "Failed to allocate flex parser data.");
748 : 0 : rte_errno = ENOMEM;
749 : 0 : return NULL;
750 : : }
751 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
752 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
753 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
754 : : MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
755 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_mode,
756 : : data->header_length_mode);
757 [ # # ]: 0 : MLX5_SET64(parse_graph_flex, flex, modify_field_select,
758 : : data->modify_field_select);
759 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_base_value,
760 : : data->header_length_base_value);
761 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
762 : : data->header_length_field_offset);
763 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
764 : : data->header_length_field_shift);
765 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, next_header_field_offset,
766 : : data->next_header_field_offset);
767 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, next_header_field_size,
768 : : data->next_header_field_size);
769 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
770 : : data->header_length_field_mask);
771 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
772 : : struct mlx5_devx_match_sample_attr *s = &data->sample[i];
773 : 0 : void *s_off = (void *)((char *)sample + i *
774 : : MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
775 : :
776 [ # # ]: 0 : if (!s->flow_match_sample_en)
777 : 0 : continue;
778 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
779 : : flow_match_sample_en, !!s->flow_match_sample_en);
780 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
781 : : flow_match_sample_field_offset,
782 : : s->flow_match_sample_field_offset);
783 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
784 : : flow_match_sample_offset_mode,
785 : : s->flow_match_sample_offset_mode);
786 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
787 : : flow_match_sample_field_offset_mask,
788 : : s->flow_match_sample_field_offset_mask);
789 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
790 : : flow_match_sample_field_offset_shift,
791 : : s->flow_match_sample_field_offset_shift);
792 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
793 : : flow_match_sample_field_base_offset,
794 : : s->flow_match_sample_field_base_offset);
795 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
796 : : flow_match_sample_tunnel_mode,
797 : : s->flow_match_sample_tunnel_mode);
798 : : }
799 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
800 : : struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
801 : : struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
802 : 0 : void *in_off = (void *)((char *)in_arc + i *
803 : : MLX5_ST_SZ_BYTES(parse_graph_arc));
804 : 0 : void *out_off = (void *)((char *)out_arc + i *
805 : : MLX5_ST_SZ_BYTES(parse_graph_arc));
806 : :
807 [ # # ]: 0 : if (ia->arc_parse_graph_node != 0) {
808 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off,
809 : : compare_condition_value,
810 : : ia->compare_condition_value);
811 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
812 : : ia->start_inner_tunnel);
813 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
814 : : ia->arc_parse_graph_node);
815 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off,
816 : : parse_graph_node_handle,
817 : : ia->parse_graph_node_handle);
818 : : }
819 [ # # ]: 0 : if (oa->arc_parse_graph_node != 0) {
820 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off,
821 : : compare_condition_value,
822 : : oa->compare_condition_value);
823 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
824 : : oa->start_inner_tunnel);
825 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
826 : : oa->arc_parse_graph_node);
827 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off,
828 : : parse_graph_node_handle,
829 : : oa->parse_graph_node_handle);
830 : : }
831 : : }
832 : 0 : parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
833 : : out, sizeof(out));
834 [ # # ]: 0 : if (!parse_flex_obj->obj) {
835 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0);
836 : 0 : mlx5_free(parse_flex_obj);
837 : 0 : return NULL;
838 : : }
839 [ # # ]: 0 : parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
840 : 0 : return parse_flex_obj;
841 : : }
842 : :
843 : : static int
844 : 0 : mlx5_devx_cmd_query_hca_parse_graph_node_cap
845 : : (void *ctx, struct mlx5_hca_flex_attr *attr)
846 : : {
847 : : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
848 : : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
849 : : void *hcattr;
850 : : int rc;
851 : :
852 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
853 : : MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP |
854 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
855 [ # # ]: 0 : if (!hcattr)
856 : 0 : return rc;
857 [ # # ]: 0 : attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in);
858 [ # # ]: 0 : attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out);
859 [ # # ]: 0 : attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr,
860 : : header_length_mode);
861 [ # # ]: 0 : attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr,
862 : : sample_offset_mode);
863 [ # # ]: 0 : attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr,
864 : : max_num_arc_in);
865 [ # # ]: 0 : attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr,
866 : : max_num_arc_out);
867 [ # # ]: 0 : attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr,
868 : : max_num_sample);
869 [ # # ]: 0 : attr->parse_graph_anchor = MLX5_GET(parse_graph_node_cap, hcattr, parse_graph_anchor);
870 [ # # ]: 0 : attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr,
871 : : sample_tunnel_inner2);
872 [ # # ]: 0 : attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr,
873 : : zero_size_supported);
874 [ # # ]: 0 : attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr,
875 : : sample_id_in_out);
876 [ # # ]: 0 : attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr,
877 : : max_base_header_length);
878 [ # # ]: 0 : attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr,
879 : : max_sample_base_offset);
880 [ # # ]: 0 : attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr,
881 : : max_next_header_offset);
882 [ # # ]: 0 : attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr,
883 : : header_length_mask_width);
884 : : /* Get the max supported samples from HCA CAP 2 */
885 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
886 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
887 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
888 [ # # ]: 0 : if (!hcattr)
889 : 0 : return rc;
890 : 0 : attr->max_num_prog_sample =
891 [ # # ]: 0 : MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field);
892 : 0 : return 0;
893 : : }
894 : :
895 : : static int
896 : 0 : mlx5_devx_query_pkt_integrity_match(void *hcattr)
897 : : {
898 [ # # ]: 0 : return MLX5_GET(flow_table_nic_cap, hcattr,
899 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l3_ok) &&
900 : : MLX5_GET(flow_table_nic_cap, hcattr,
901 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l4_ok) &&
902 : : MLX5_GET(flow_table_nic_cap, hcattr,
903 [ # # # # ]: 0 : ft_field_support_2_nic_receive.outer_l3_ok) &&
904 : : MLX5_GET(flow_table_nic_cap, hcattr,
905 [ # # # # ]: 0 : ft_field_support_2_nic_receive.outer_l4_ok) &&
906 : : MLX5_GET(flow_table_nic_cap, hcattr,
907 : : ft_field_support_2_nic_receive
908 [ # # # # ]: 0 : .inner_ipv4_checksum_ok) &&
909 : : MLX5_GET(flow_table_nic_cap, hcattr,
910 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l4_checksum_ok) &&
911 : : MLX5_GET(flow_table_nic_cap, hcattr,
912 : : ft_field_support_2_nic_receive
913 [ # # # # : 0 : .outer_ipv4_checksum_ok) &&
# # # # #
# # # # #
# # # # ]
914 [ # # # # ]: 0 : MLX5_GET(flow_table_nic_cap, hcattr,
915 : : ft_field_support_2_nic_receive.outer_l4_checksum_ok);
916 : : }
917 : :
918 : : /**
919 : : * Query HCA attributes.
920 : : * Using those attributes we can check on run time if the device
921 : : * is having the required capabilities.
922 : : *
923 : : * @param[in] ctx
924 : : * Context returned from mlx5 open_device() glue function.
925 : : * @param[out] attr
926 : : * Attributes device values.
927 : : *
928 : : * @return
929 : : * 0 on success, a negative value otherwise.
930 : : */
931 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_hca_attr)
932 : : int
933 : 0 : mlx5_devx_cmd_query_hca_attr(void *ctx,
934 : : struct mlx5_hca_attr *attr)
935 : : {
936 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
937 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
938 : : bool hca_cap_2_sup;
939 : : uint64_t general_obj_types_supported = 0;
940 : : uint64_t stc_action_type_127_64;
941 : : void *hcattr;
942 : : int rc, i;
943 : :
944 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
945 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
946 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
947 [ # # ]: 0 : if (!hcattr)
948 : 0 : return rc;
949 [ # # ]: 0 : hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2);
950 [ # # ]: 0 : attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq);
951 : 0 : attr->flow_counter_bulk_alloc_bitmap =
952 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
953 [ # # ]: 0 : attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
954 : : flow_counters_dump);
955 [ # # ]: 0 : attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp);
956 [ # # ]: 0 : attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp);
957 [ # # ]: 0 : attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
958 : : log_max_rqt_size);
959 [ # # ]: 0 : attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
960 [ # # ]: 0 : attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
961 [ # # ]: 0 : attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
962 : : log_max_hairpin_queues);
963 [ # # ]: 0 : attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
964 : : log_max_hairpin_wq_data_sz);
965 [ # # ]: 0 : attr->log_max_hairpin_num_packets = MLX5_GET
966 : : (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
967 [ # # ]: 0 : attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
968 [ # # ]: 0 : attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
969 : : relaxed_ordering_write);
970 [ # # ]: 0 : attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
971 : : relaxed_ordering_read);
972 [ # # ]: 0 : attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
973 : : access_register_user);
974 [ # # ]: 0 : attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
975 : : eth_net_offloads);
976 [ # # ]: 0 : attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
977 [ # # ]: 0 : attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
978 : : flex_parser_protocols);
979 [ # # ]: 0 : attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
980 : : max_geneve_tlv_options);
981 [ # # ]: 0 : attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
982 : : max_geneve_tlv_option_data_len);
983 [ # # ]: 0 : attr->geneve_tlv_option_offset = MLX5_GET(cmd_hca_cap, hcattr,
984 : : geneve_tlv_option_offset);
985 [ # # ]: 0 : attr->geneve_tlv_sample = MLX5_GET(cmd_hca_cap, hcattr,
986 : : geneve_tlv_sample);
987 [ # # ]: 0 : attr->query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr,
988 : : query_match_sample_info);
989 [ # # ]: 0 : attr->geneve_tlv_option_sample_id = MLX5_GET(cmd_hca_cap, hcattr,
990 : : flex_parser_id_geneve_opt_0);
991 [ # # ]: 0 : attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
992 [ # # ]: 0 : attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
993 : : wqe_index_ignore_cap);
994 [ # # ]: 0 : attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
995 [ # # ]: 0 : attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
996 [ # # ]: 0 : attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
997 : : log_max_static_sq_wq);
998 [ # # ]: 0 : attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
999 [ # # ]: 0 : attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
1000 : : device_frequency_khz);
1001 : 0 : attr->scatter_fcs_w_decap_disable =
1002 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
1003 [ # # ]: 0 : attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
1004 [ # # ]: 0 : attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
1005 [ # # ]: 0 : attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
1006 : 0 : attr->steering_format_version =
1007 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, steering_format_version);
1008 [ # # ]: 0 : attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params);
1009 [ # # ]: 0 : attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version);
1010 [ # # ]: 0 : attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
1011 : : regexp_num_of_engines);
1012 : : /* Read the general_obj_types bitmap and extract the relevant bits. */
1013 [ # # ]: 0 : general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
1014 : : general_obj_types);
1015 : 0 : attr->qos.flow_meter_aso_sup =
1016 : 0 : !!(general_obj_types_supported &
1017 : : MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
1018 : 0 : attr->vdpa.valid = !!(general_obj_types_supported &
1019 : : MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
1020 : 0 : attr->vdpa.queue_counters_valid =
1021 : 0 : !!(general_obj_types_supported &
1022 : : MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
1023 : 0 : attr->parse_graph_flex_node =
1024 : 0 : !!(general_obj_types_supported &
1025 : : MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
1026 : 0 : attr->flow_hit_aso = !!(general_obj_types_supported &
1027 : : MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
1028 : 0 : attr->geneve_tlv_opt = !!(general_obj_types_supported &
1029 : : MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
1030 : 0 : attr->dek = !!(general_obj_types_supported &
1031 : : MLX5_GENERAL_OBJ_TYPES_CAP_DEK);
1032 : 0 : attr->import_kek = !!(general_obj_types_supported &
1033 : : MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK);
1034 : 0 : attr->credential = !!(general_obj_types_supported &
1035 : : MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL);
1036 : 0 : attr->crypto_login = !!(general_obj_types_supported &
1037 : : MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN);
1038 : : /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
1039 [ # # ]: 0 : attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
1040 [ # # ]: 0 : attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
1041 [ # # ]: 0 : attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
1042 [ # # ]: 0 : attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
1043 [ # # ]: 0 : attr->log_max_wq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_wq_sz);
1044 [ # # ]: 0 : attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
1045 [ # # ]: 0 : attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
1046 [ # # ]: 0 : attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
1047 [ # # ]: 0 : attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
1048 : 0 : attr->reg_c_preserve =
1049 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
1050 [ # # ]: 0 : attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp);
1051 [ # # ]: 0 : attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq);
1052 [ # # ]: 0 : attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq);
1053 [ # # ]: 0 : attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
1054 : : compress_mmo_sq);
1055 [ # # ]: 0 : attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
1056 : : decompress_mmo_sq);
1057 [ # # ]: 0 : attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp);
1058 [ # # ]: 0 : attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,
1059 : : compress_mmo_qp);
1060 [ # # ]: 0 : attr->decomp_deflate_v1_en = MLX5_GET(cmd_hca_cap, hcattr,
1061 : : decompress_deflate_v1);
1062 [ # # ]: 0 : attr->decomp_deflate_v2_en = MLX5_GET(cmd_hca_cap, hcattr,
1063 : : decompress_deflate_v2);
1064 [ # # ]: 0 : attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
1065 : : compress_min_block_size);
1066 [ # # ]: 0 : attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
1067 [ # # ]: 0 : attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
1068 : : log_compress_mmo_size);
1069 [ # # ]: 0 : attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
1070 : : log_decompress_mmo_size);
1071 [ # # ]: 0 : attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr,
1072 : : decompress_lz4_data_only_v2);
1073 [ # # ]: 0 : attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr,
1074 : : decompress_lz4_no_checksum_v2);
1075 [ # # ]: 0 : attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr,
1076 : : decompress_lz4_checksum_v2);
1077 [ # # ]: 0 : attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
1078 [ # # ]: 0 : attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
1079 : : mini_cqe_resp_flow_tag);
1080 [ # # ]: 0 : attr->cqe_compression_128 = MLX5_GET(cmd_hca_cap, hcattr,
1081 : : cqe_compression_128);
1082 [ # # ]: 0 : attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
1083 : : mini_cqe_resp_l3_l4_tag);
1084 [ # # ]: 0 : attr->enhanced_cqe_compression = MLX5_GET(cmd_hca_cap, hcattr,
1085 : : enhanced_cqe_compression);
1086 : 0 : attr->umr_indirect_mkey_disabled =
1087 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
1088 : 0 : attr->umr_modify_entity_size_disabled =
1089 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
1090 [ # # ]: 0 : attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time);
1091 [ # # ]: 0 : attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
1092 : 0 : attr->ct_offload = !!(general_obj_types_supported &
1093 : : MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);
1094 [ # # ]: 0 : attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop);
1095 [ # # ]: 0 : attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table);
1096 [ # # ]: 0 : attr->striding_rq = MLX5_GET(cmd_hca_cap, hcattr, striding_rq);
1097 : 0 : attr->ext_stride_num_range =
1098 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, ext_stride_num_range);
1099 [ # # ]: 0 : attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table);
1100 [ # # ]: 0 : attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr,
1101 : : max_flow_counter_15_0);
1102 [ # # ]: 0 : attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr,
1103 : : max_flow_counter_31_16);
1104 [ # # ]: 0 : attr->alloc_flow_counter_pd = MLX5_GET(cmd_hca_cap, hcattr,
1105 : : alloc_flow_counter_pd);
1106 [ # # ]: 0 : attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr,
1107 : : flow_counter_access_aso);
1108 [ # # ]: 0 : attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr,
1109 : : flow_access_aso_opc_mod);
1110 [ # # ]: 0 : attr->wqe_based_flow_table_sup = MLX5_GET(cmd_hca_cap, hcattr,
1111 : : wqe_based_flow_table_update_cap);
1112 : : /*
1113 : : * Flex item support needs max_num_prog_sample_field
1114 : : * from the Capabilities 2 table for PARSE_GRAPH_NODE
1115 : : */
1116 [ # # ]: 0 : if (attr->parse_graph_flex_node) {
1117 : 0 : rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap
1118 : : (ctx, &attr->flex);
1119 [ # # ]: 0 : if (rc)
1120 : : return -1;
1121 : 0 : attr->flex.query_match_sample_info =
1122 : 0 : attr->query_match_sample_info;
1123 : : }
1124 [ # # ]: 0 : if (attr->crypto) {
1125 [ # # # # : 0 : attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) ||
# # ]
1126 [ # # # # : 0 : MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) ||
# # # # #
# # # ]
1127 : : MLX5_GET(cmd_hca_cap, hcattr, aes_xts_single_block_le_tweak);
1128 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1129 : : MLX5_GET_HCA_CAP_OP_MOD_CRYPTO |
1130 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1131 [ # # ]: 0 : if (!hcattr)
1132 : : return -1;
1133 [ # # ]: 0 : attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps,
1134 : : hcattr, wrapped_import_method)
1135 : 0 : & 1 << 2);
1136 [ # # ]: 0 : attr->crypto_mmo.crypto_mmo_qp = MLX5_GET(crypto_caps, hcattr, crypto_mmo_qp);
1137 : 0 : attr->crypto_mmo.gcm_256_encrypt =
1138 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_encrypt);
1139 : 0 : attr->crypto_mmo.gcm_128_encrypt =
1140 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_encrypt);
1141 : 0 : attr->crypto_mmo.gcm_256_decrypt =
1142 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_decrypt);
1143 : 0 : attr->crypto_mmo.gcm_128_decrypt =
1144 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_decrypt);
1145 : 0 : attr->crypto_mmo.gcm_auth_tag_128 =
1146 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_128);
1147 : 0 : attr->crypto_mmo.gcm_auth_tag_96 =
1148 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_96);
1149 : 0 : attr->crypto_mmo.log_crypto_mmo_max_size =
1150 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, log_crypto_mmo_max_size);
1151 : : }
1152 [ # # ]: 0 : if (hca_cap_2_sup) {
1153 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1154 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
1155 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1156 [ # # ]: 0 : if (!hcattr) {
1157 : 0 : DRV_LOG(DEBUG,
1158 : : "Failed to query DevX HCA capabilities 2.");
1159 : 0 : return rc;
1160 : : }
1161 [ # # ]: 0 : attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr,
1162 : : log_min_stride_wqe_sz);
1163 [ # # ]: 0 : attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr,
1164 : : hairpin_sq_wqe_bb_size);
1165 [ # # ]: 0 : attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr,
1166 : : hairpin_sq_wq_in_host_mem);
1167 [ # # ]: 0 : attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr,
1168 : : hairpin_data_buffer_locked);
1169 [ # # ]: 0 : attr->flow_counter_bulk_log_max_alloc = MLX5_GET(cmd_hca_cap_2,
1170 : : hcattr, flow_counter_bulk_log_max_alloc);
1171 : 0 : attr->flow_counter_bulk_log_granularity =
1172 [ # # ]: 0 : MLX5_GET(cmd_hca_cap_2, hcattr,
1173 : : flow_counter_bulk_log_granularity);
1174 [ # # ]: 0 : rc = MLX5_GET(cmd_hca_cap_2, hcattr,
1175 : : cross_vhca_object_to_object_supported);
1176 : 0 : attr->cross_vhca =
1177 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR) &&
1178 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT) &&
1179 : 0 : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT) &&
1180 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC);
1181 [ # # ]: 0 : rc = MLX5_GET(cmd_hca_cap_2, hcattr,
1182 : : allowed_object_for_other_vhca_access);
1183 : 0 : attr->cross_vhca = attr->cross_vhca &&
1184 : : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR) &&
1185 [ # # # # ]: 0 : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) &&
1186 : : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC);
1187 [ # # ]: 0 : if (attr->ct_offload)
1188 [ # # ]: 0 : attr->log_max_conn_track_offload = MLX5_GET(cmd_hca_cap_2, hcattr,
1189 : : log_max_conn_track_offload);
1190 : : }
1191 [ # # ]: 0 : if (attr->log_min_stride_wqe_sz == 0)
1192 : 0 : attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;
1193 [ # # ]: 0 : if (attr->qos.sup) {
1194 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1195 : : MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
1196 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1197 [ # # ]: 0 : if (!hcattr) {
1198 : 0 : DRV_LOG(DEBUG, "Failed to query devx QOS capabilities");
1199 : 0 : return rc;
1200 : : }
1201 : 0 : attr->qos.flow_meter_old =
1202 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, flow_meter_old);
1203 [ # # ]: 0 : attr->qos.log_max_flow_meter =
1204 : 0 : MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
1205 [ # # ]: 0 : attr->qos.flow_meter_reg_c_ids =
1206 : : MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
1207 : 0 : attr->qos.flow_meter =
1208 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, flow_meter);
1209 : 0 : attr->qos.packet_pacing =
1210 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, packet_pacing);
1211 : 0 : attr->qos.wqe_rate_pp =
1212 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
1213 [ # # ]: 0 : if (attr->qos.flow_meter_aso_sup) {
1214 : 0 : attr->qos.log_meter_aso_granularity =
1215 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1216 : : log_meter_aso_granularity);
1217 : 0 : attr->qos.log_meter_aso_max_alloc =
1218 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1219 : : log_meter_aso_max_alloc);
1220 : 0 : attr->qos.log_max_num_meter_aso =
1221 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1222 : : log_max_num_meter_aso);
1223 : : }
1224 : : }
1225 [ # # ]: 0 : if (attr->vdpa.valid)
1226 : 0 : mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
1227 [ # # ]: 0 : if (!attr->eth_net_offloads)
1228 : : return 0;
1229 : : /* Query Flow Sampler Capability From FLow Table Properties Layout. */
1230 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1231 : : MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
1232 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1233 [ # # ]: 0 : if (!hcattr) {
1234 : 0 : attr->log_max_ft_sampler_num = 0;
1235 : 0 : return rc;
1236 : : }
1237 [ # # ]: 0 : attr->log_max_ft_sampler_num = MLX5_GET
1238 : : (flow_table_nic_cap, hcattr,
1239 : : flow_table_properties_nic_receive.log_max_ft_sampler_num);
1240 [ # # ]: 0 : attr->flow.tunnel_header_0_1 = MLX5_GET
1241 : : (flow_table_nic_cap, hcattr,
1242 : : ft_field_support_2_nic_receive.tunnel_header_0_1);
1243 [ # # ]: 0 : attr->flow.tunnel_header_2_3 = MLX5_GET
1244 : : (flow_table_nic_cap, hcattr,
1245 : : ft_field_support_2_nic_receive.tunnel_header_2_3);
1246 [ # # ]: 0 : attr->modify_outer_ip_ecn = MLX5_GET
1247 : : (flow_table_nic_cap, hcattr,
1248 : : ft_header_modify_nic_receive.outer_ip_ecn);
1249 [ # # ]: 0 : attr->modify_outer_ipv6_traffic_class = MLX5_GET
1250 : : (flow_table_nic_cap, hcattr,
1251 : : ft_header_modify_nic_receive.outer_ipv6_traffic_class);
1252 : 0 : attr->set_reg_c = 0xffff;
1253 [ # # ]: 0 : if (attr->nic_flow_table) {
1254 : : #define GET_RX_REG_X_BITS \
1255 : : MLX5_GET(flow_table_nic_cap, hcattr, \
1256 : : ft_header_modify_nic_receive.metadata_reg_c_x)
1257 : : #define GET_TX_REG_X_BITS \
1258 : : MLX5_GET(flow_table_nic_cap, hcattr, \
1259 : : ft_header_modify_nic_transmit.metadata_reg_c_x)
1260 : :
1261 : : uint32_t tx_reg, rx_reg, reg_c_8_15;
1262 : :
1263 [ # # ]: 0 : tx_reg = GET_TX_REG_X_BITS;
1264 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr,
1265 : : ft_field_support_2_nic_transmit.metadata_reg_c_8_15);
1266 : 0 : tx_reg |= ((0xff & reg_c_8_15) << 8);
1267 [ # # ]: 0 : rx_reg = GET_RX_REG_X_BITS;
1268 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr,
1269 : : ft_field_support_2_nic_receive.metadata_reg_c_8_15);
1270 : 0 : rx_reg |= ((0xff & reg_c_8_15) << 8);
1271 : 0 : attr->set_reg_c &= (rx_reg & tx_reg);
1272 : :
1273 : : #undef GET_RX_REG_X_BITS
1274 : : #undef GET_TX_REG_X_BITS
1275 : : }
1276 : 0 : attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
1277 [ # # ]: 0 : attr->inner_ipv4_ihl = MLX5_GET
1278 : : (flow_table_nic_cap, hcattr,
1279 : : ft_field_support_2_nic_receive.inner_ipv4_ihl);
1280 [ # # ]: 0 : attr->outer_ipv4_ihl = MLX5_GET
1281 : : (flow_table_nic_cap, hcattr,
1282 : : ft_field_support_2_nic_receive.outer_ipv4_ihl);
1283 [ # # ]: 0 : attr->lag_rx_port_affinity = MLX5_GET
1284 : : (flow_table_nic_cap, hcattr,
1285 : : ft_field_support_2_nic_receive.lag_rx_port_affinity);
1286 : : /* Query HCA offloads for Ethernet protocol. */
1287 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1288 : : MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
1289 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1290 [ # # ]: 0 : if (!hcattr) {
1291 : 0 : attr->eth_net_offloads = 0;
1292 : 0 : return rc;
1293 : : }
1294 [ # # ]: 0 : attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
1295 : : hcattr, wqe_vlan_insert);
1296 [ # # ]: 0 : attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,
1297 : : hcattr, csum_cap);
1298 [ # # ]: 0 : attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps,
1299 : : hcattr, vlan_cap);
1300 [ # # ]: 0 : attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1301 : : lro_cap);
1302 [ # # ]: 0 : attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps,
1303 : : hcattr, max_lso_cap);
1304 [ # # ]: 0 : attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps,
1305 : : hcattr, scatter_fcs);
1306 [ # # ]: 0 : attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
1307 : : hcattr, tunnel_lro_gre);
1308 [ # # ]: 0 : attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
1309 : : hcattr, tunnel_lro_vxlan);
1310 [ # # ]: 0 : attr->swp = MLX5_GET(per_protocol_networking_offload_caps,
1311 : : hcattr, swp);
1312 : 0 : attr->tunnel_stateless_gre =
1313 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1314 : : hcattr, tunnel_stateless_gre);
1315 : 0 : attr->tunnel_stateless_vxlan =
1316 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1317 : : hcattr, tunnel_stateless_vxlan);
1318 [ # # ]: 0 : attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps,
1319 : : hcattr, swp_csum);
1320 [ # # ]: 0 : attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps,
1321 : : hcattr, swp_lso);
1322 [ # # ]: 0 : attr->lro_max_msg_sz_mode = MLX5_GET
1323 : : (per_protocol_networking_offload_caps,
1324 : : hcattr, lro_max_msg_sz_mode);
1325 [ # # ]: 0 : for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
1326 : 0 : attr->lro_timer_supported_periods[i] =
1327 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1328 : : lro_timer_supported_periods[i]);
1329 : : }
1330 [ # # ]: 0 : attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
1331 : : hcattr, lro_min_mss_size);
1332 : 0 : attr->tunnel_stateless_geneve_rx =
1333 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1334 : : hcattr, tunnel_stateless_geneve_rx);
1335 : 0 : attr->geneve_max_opt_len =
1336 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1337 : : hcattr, max_geneve_opt_len);
1338 [ # # ]: 0 : attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
1339 : : hcattr, wqe_inline_mode);
1340 [ # # ]: 0 : attr->tunnel_stateless_gtp = MLX5_GET
1341 : : (per_protocol_networking_offload_caps,
1342 : : hcattr, tunnel_stateless_gtp);
1343 [ # # ]: 0 : attr->tunnel_stateless_vxlan_gpe_nsh = MLX5_GET
1344 : : (per_protocol_networking_offload_caps,
1345 : : hcattr, tunnel_stateless_vxlan_gpe_nsh);
1346 [ # # ]: 0 : attr->rss_ind_tbl_cap = MLX5_GET
1347 : : (per_protocol_networking_offload_caps,
1348 : : hcattr, rss_ind_tbl_cap);
1349 [ # # ]: 0 : attr->multi_pkt_send_wqe = MLX5_GET
1350 : : (per_protocol_networking_offload_caps,
1351 : : hcattr, multi_pkt_send_wqe);
1352 [ # # ]: 0 : attr->enhanced_multi_pkt_send_wqe = MLX5_GET
1353 : : (per_protocol_networking_offload_caps,
1354 : : hcattr, enhanced_multi_pkt_send_wqe);
1355 [ # # ]: 0 : if (attr->wqe_based_flow_table_sup) {
1356 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1357 : : MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE |
1358 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1359 [ # # ]: 0 : if (!hcattr) {
1360 : 0 : DRV_LOG(DEBUG, "Failed to query WQE Based Flow table capabilities");
1361 : 0 : return rc;
1362 : : }
1363 [ # # ]: 0 : attr->max_header_modify_pattern_length = MLX5_GET(wqe_based_flow_table_cap,
1364 : : hcattr,
1365 : : max_header_modify_pattern_length);
1366 [ # # ]: 0 : attr->fdb_unified_en = MLX5_GET(wqe_based_flow_table_cap,
1367 : : hcattr,
1368 : : fdb_unified_en);
1369 [ # # ]: 0 : stc_action_type_127_64 = MLX5_GET64(wqe_based_flow_table_cap,
1370 : : hcattr,
1371 : : stc_action_type_127_64);
1372 [ # # ]: 0 : if (stc_action_type_127_64 &
1373 : : (1 << (MLX5_IFC_STC_ACTION_TYPE_JUMP_FLOW_TABLE_FDB_RX_BIT_INDEX -
1374 : : MLX5_IFC_STC_ACTION_TYPE_BIT_64_INDEX)))
1375 : 0 : attr->jump_fdb_rx_en = 1;
1376 : : }
1377 : : /* Query HCA attribute for ROCE. */
1378 [ # # ]: 0 : if (attr->roce) {
1379 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1380 : : MLX5_GET_HCA_CAP_OP_MOD_ROCE |
1381 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1382 [ # # ]: 0 : if (!hcattr) {
1383 : 0 : DRV_LOG(DEBUG,
1384 : : "Failed to query devx HCA ROCE capabilities");
1385 : 0 : return rc;
1386 : : }
1387 [ # # ]: 0 : attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
1388 : : }
1389 [ # # ]: 0 : if (attr->eth_virt) {
1390 : 0 : rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
1391 [ # # ]: 0 : if (rc) {
1392 : 0 : attr->eth_virt = 0;
1393 : 0 : goto error;
1394 : : }
1395 : : }
1396 [ # # ]: 0 : if (attr->eswitch_manager) {
1397 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1398 : : MLX5_SET_HCA_CAP_OP_MOD_ESW |
1399 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1400 [ # # ]: 0 : if (!hcattr)
1401 : 0 : return rc;
1402 : 0 : attr->esw_mgr_vport_id_valid =
1403 [ # # ]: 0 : MLX5_GET(esw_cap, hcattr,
1404 : : esw_manager_vport_number_valid);
1405 : 0 : attr->esw_mgr_vport_id =
1406 [ # # ]: 0 : MLX5_GET(esw_cap, hcattr, esw_manager_vport_number);
1407 : : }
1408 [ # # ]: 0 : if (attr->eswitch_manager) {
1409 : : uint32_t esw_reg, reg_c_8_15;
1410 : :
1411 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1412 : : MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE |
1413 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1414 [ # # ]: 0 : if (!hcattr)
1415 : 0 : return rc;
1416 [ # # ]: 0 : esw_reg = MLX5_GET(flow_table_esw_cap, hcattr,
1417 : : ft_header_modify_esw_fdb.metadata_reg_c_x);
1418 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_esw_cap, hcattr,
1419 : : ft_field_support_2_esw_fdb.metadata_reg_c_8_15);
1420 : 0 : attr->set_reg_c &= ((0xff & reg_c_8_15) << 8) | esw_reg;
1421 : : }
1422 : : return 0;
1423 : : error:
1424 : 0 : rc = (rc > 0) ? -rc : rc;
1425 : 0 : return rc;
1426 : : }
1427 : :
1428 : : /**
1429 : : * Query TIS transport domain from QP verbs object using DevX API.
1430 : : *
1431 : : * @param[in] qp
1432 : : * Pointer to verbs QP returned by ibv_create_qp .
1433 : : * @param[in] tis_num
1434 : : * TIS number of TIS to query.
1435 : : * @param[out] tis_td
1436 : : * Pointer to TIS transport domain variable, to be set by the routine.
1437 : : *
1438 : : * @return
1439 : : * 0 on success, a negative value otherwise.
1440 : : */
1441 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_qp_query_tis_td)
1442 : : int
1443 : 0 : mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
1444 : : uint32_t *tis_td)
1445 : : {
1446 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1447 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
1448 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
1449 : : int rc;
1450 : : void *tis_ctx;
1451 : :
1452 : 0 : MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
1453 : 0 : MLX5_SET(query_tis_in, in, tisn, tis_num);
1454 : 0 : rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
1455 [ # # ]: 0 : if (rc) {
1456 : 0 : DRV_LOG(ERR, "Failed to query QP using DevX");
1457 : 0 : return -rc;
1458 : : };
1459 : : tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
1460 [ # # ]: 0 : *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
1461 : 0 : return 0;
1462 : : #else
1463 : : (void)qp;
1464 : : (void)tis_num;
1465 : : (void)tis_td;
1466 : : return -ENOTSUP;
1467 : : #endif
1468 : : }
1469 : :
1470 : : /**
1471 : : * Fill WQ data for DevX API command.
1472 : : * Utility function for use when creating DevX objects containing a WQ.
1473 : : *
1474 : : * @param[in] wq_ctx
1475 : : * Pointer to WQ context to fill with data.
1476 : : * @param [in] wq_attr
1477 : : * Pointer to WQ attributes structure to fill in WQ context.
1478 : : */
1479 : : static void
1480 : 0 : devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
1481 : : {
1482 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
1483 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
1484 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
1485 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
1486 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
1487 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
1488 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
1489 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
1490 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
1491 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
1492 [ # # ]: 0 : MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1493 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1494 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1495 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1496 [ # # ]: 0 : if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1497 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1498 : : wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1499 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1500 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1501 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1502 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1503 : : wq_attr->log_hairpin_num_packets);
1504 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1505 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1506 : : wq_attr->single_wqe_log_num_of_strides);
1507 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1508 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1509 : : wq_attr->single_stride_log_num_of_bytes);
1510 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1511 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1512 [ # # ]: 0 : MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1513 : 0 : }
1514 : :
1515 : : /**
1516 : : * Create RQ using DevX API.
1517 : : *
1518 : : * @param[in] ctx
1519 : : * Context returned from mlx5 open_device() glue function.
1520 : : * @param [in] rq_attr
1521 : : * Pointer to create RQ attributes structure.
1522 : : * @param [in] socket
1523 : : * CPU socket ID for allocations.
1524 : : *
1525 : : * @return
1526 : : * The DevX object created, NULL otherwise and rte_errno is set.
1527 : : */
1528 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_rq)
1529 : : struct mlx5_devx_obj *
1530 : 0 : mlx5_devx_cmd_create_rq(void *ctx,
1531 : : struct mlx5_devx_create_rq_attr *rq_attr,
1532 : : int socket)
1533 : : {
1534 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1535 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1536 : : void *rq_ctx, *wq_ctx;
1537 : : struct mlx5_devx_wq_attr *wq_attr;
1538 : : struct mlx5_devx_obj *rq = NULL;
1539 : :
1540 : 0 : rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1541 [ # # ]: 0 : if (!rq) {
1542 : 0 : DRV_LOG(ERR, "Failed to allocate RQ data");
1543 : 0 : rte_errno = ENOMEM;
1544 : 0 : return NULL;
1545 : : }
1546 [ # # ]: 0 : MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1547 : : rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1548 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1549 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1550 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1551 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1552 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1553 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1554 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1555 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1556 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type);
1557 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1558 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1559 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1560 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1561 [ # # ]: 0 : MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1562 : : wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1563 : 0 : wq_attr = &rq_attr->wq_attr;
1564 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1565 : 0 : rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1566 : : out, sizeof(out));
1567 [ # # ]: 0 : if (!rq->obj) {
1568 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0);
1569 : 0 : mlx5_free(rq);
1570 : 0 : return NULL;
1571 : : }
1572 [ # # ]: 0 : rq->id = MLX5_GET(create_rq_out, out, rqn);
1573 : 0 : return rq;
1574 : : }
1575 : :
1576 : : /**
1577 : : * Modify RQ using DevX API.
1578 : : *
1579 : : * @param[in] rq
1580 : : * Pointer to RQ object structure.
1581 : : * @param [in] rq_attr
1582 : : * Pointer to modify RQ attributes structure.
1583 : : *
1584 : : * @return
1585 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
1586 : : */
1587 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_rq)
1588 : : int
1589 : 0 : mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1590 : : struct mlx5_devx_modify_rq_attr *rq_attr)
1591 : : {
1592 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1593 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1594 : : void *rq_ctx, *wq_ctx;
1595 : : int ret;
1596 : :
1597 : 0 : MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1598 : 0 : MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1599 [ # # ]: 0 : MLX5_SET(modify_rq_in, in, rqn, rq->id);
1600 [ # # ]: 0 : MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1601 : : rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1602 : 0 : MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1603 [ # # ]: 0 : if (rq_attr->modify_bitmask &
1604 : : MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1605 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1606 [ # # ]: 0 : if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1607 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1608 [ # # ]: 0 : if (rq_attr->modify_bitmask &
1609 : : MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1610 : 0 : MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1611 : 0 : MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1612 : 0 : MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1613 [ # # ]: 0 : if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1614 : : wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1615 : 0 : MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1616 : : }
1617 : 0 : ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1618 : : out, sizeof(out));
1619 : :
1620 [ # # ]: 0 : if (ret) {
1621 : 0 : DRV_LOG(ERR, "Failed to modify RQ using DevX");
1622 : 0 : rte_errno = errno;
1623 : 0 : return -errno;
1624 : : }
1625 : : return ret;
1626 : : }
1627 : :
1628 : : /*
1629 : : * Query RQ using DevX API.
1630 : : *
1631 : : * @param[in] rq_obj
1632 : : * RQ Devx Object
1633 : : * @param[out] out
1634 : : * RQ Query Output
1635 : : * @param[in] outlen
1636 : : * RQ Query Output Length
1637 : : *
1638 : : * @return
1639 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
1640 : : */
1641 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_rq)
1642 : : int
1643 : 0 : mlx5_devx_cmd_query_rq(struct mlx5_devx_obj *rq_obj, void *out, size_t outlen)
1644 : : {
1645 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
1646 : : int rc;
1647 : :
1648 : 0 : MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
1649 : 0 : MLX5_SET(query_rq_in, in, rqn, rq_obj->id);
1650 : 0 : rc = mlx5_glue->devx_obj_query(rq_obj->obj, in, sizeof(in), out, outlen);
1651 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
1652 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "RQ query", "rq_id", rq_obj->id);
1653 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
1654 : : }
1655 : : return 0;
1656 : : }
1657 : :
1658 : : /**
1659 : : * Create RMP using DevX API.
1660 : : *
1661 : : * @param[in] ctx
1662 : : * Context returned from mlx5 open_device() glue function.
1663 : : * @param [in] rmp_attr
1664 : : * Pointer to create RMP attributes structure.
1665 : : * @param [in] socket
1666 : : * CPU socket ID for allocations.
1667 : : *
1668 : : * @return
1669 : : * The DevX object created, NULL otherwise and rte_errno is set.
1670 : : */
1671 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_rmp)
1672 : : struct mlx5_devx_obj *
1673 : 0 : mlx5_devx_cmd_create_rmp(void *ctx,
1674 : : struct mlx5_devx_create_rmp_attr *rmp_attr,
1675 : : int socket)
1676 : : {
1677 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0};
1678 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0};
1679 : : void *rmp_ctx, *wq_ctx;
1680 : : struct mlx5_devx_wq_attr *wq_attr;
1681 : : struct mlx5_devx_obj *rmp = NULL;
1682 : :
1683 : 0 : rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket);
1684 [ # # ]: 0 : if (!rmp) {
1685 : 0 : DRV_LOG(ERR, "Failed to allocate RMP data");
1686 : 0 : rte_errno = ENOMEM;
1687 : 0 : return NULL;
1688 : : }
1689 [ # # ]: 0 : MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP);
1690 : : rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx);
1691 [ # # ]: 0 : MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state);
1692 [ # # ]: 0 : MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe,
1693 : : rmp_attr->basic_cyclic_rcv_wqe);
1694 : : wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq);
1695 : 0 : wq_attr = &rmp_attr->wq_attr;
1696 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1697 : 0 : rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1698 : : sizeof(out));
1699 [ # # ]: 0 : if (!rmp->obj) {
1700 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0);
1701 : 0 : mlx5_free(rmp);
1702 : 0 : return NULL;
1703 : : }
1704 [ # # ]: 0 : rmp->id = MLX5_GET(create_rmp_out, out, rmpn);
1705 : 0 : return rmp;
1706 : : }
1707 : :
1708 : : /*
1709 : : * Create TIR using DevX API.
1710 : : *
1711 : : * @param[in] ctx
1712 : : * Context returned from mlx5 open_device() glue function.
1713 : : * @param [in] tir_attr
1714 : : * Pointer to TIR attributes structure.
1715 : : *
1716 : : * @return
1717 : : * The DevX object created, NULL otherwise and rte_errno is set.
1718 : : */
1719 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_tir)
1720 : : struct mlx5_devx_obj *
1721 : 0 : mlx5_devx_cmd_create_tir(void *ctx,
1722 : : struct mlx5_devx_tir_attr *tir_attr)
1723 : : {
1724 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1725 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1726 : : void *tir_ctx, *outer, *inner, *rss_key;
1727 : : struct mlx5_devx_obj *tir = NULL;
1728 : :
1729 : 0 : tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1730 [ # # ]: 0 : if (!tir) {
1731 : 0 : DRV_LOG(ERR, "Failed to allocate TIR data");
1732 : 0 : rte_errno = ENOMEM;
1733 : 0 : return NULL;
1734 : : }
1735 [ # # ]: 0 : MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1736 : : tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1737 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1738 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1739 : : tir_attr->lro_timeout_period_usecs);
1740 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1741 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1742 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1743 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1744 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1745 : : tir_attr->tunneled_offload_en);
1746 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1747 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1748 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1749 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1750 : : rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1751 [ # # ]: 0 : memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1752 : : outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1753 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1754 : : tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1755 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1756 : : tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1757 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, selected_fields,
1758 : : tir_attr->rx_hash_field_selector_outer.selected_fields);
1759 : : inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1760 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1761 : : tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1762 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1763 : : tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1764 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, selected_fields,
1765 : : tir_attr->rx_hash_field_selector_inner.selected_fields);
1766 : 0 : tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1767 : : out, sizeof(out));
1768 [ # # ]: 0 : if (!tir->obj) {
1769 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0);
1770 : 0 : mlx5_free(tir);
1771 : 0 : return NULL;
1772 : : }
1773 [ # # ]: 0 : tir->id = MLX5_GET(create_tir_out, out, tirn);
1774 : 0 : return tir;
1775 : : }
1776 : :
1777 : : /**
1778 : : * Modify TIR using DevX API.
1779 : : *
1780 : : * @param[in] tir
1781 : : * Pointer to TIR DevX object structure.
1782 : : * @param [in] modify_tir_attr
1783 : : * Pointer to TIR modification attributes structure.
1784 : : *
1785 : : * @return
1786 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
1787 : : */
1788 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_tir)
1789 : : int
1790 : 0 : mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1791 : : struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1792 : : {
1793 : : struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1794 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1795 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1796 : : void *tir_ctx;
1797 : : int ret;
1798 : :
1799 : 0 : MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1800 : 0 : MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1801 [ # # ]: 0 : MLX5_SET64(modify_tir_in, in, modify_bitmask,
1802 : : modify_tir_attr->modify_bitmask);
1803 : : tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1804 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1805 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1806 : 0 : MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1807 : : tir_attr->lro_timeout_period_usecs);
1808 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1809 : : tir_attr->lro_enable_mask);
1810 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1811 : : tir_attr->lro_max_msg_sz);
1812 : : }
1813 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1814 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1815 : 0 : MLX5_SET(tirc, tir_ctx, indirect_table,
1816 : : tir_attr->indirect_table);
1817 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1818 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1819 : : int i;
1820 : : void *outer, *inner;
1821 : :
1822 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1823 : : tir_attr->rx_hash_symmetric);
1824 : 0 : MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1825 [ # # ]: 0 : for (i = 0; i < 10; i++) {
1826 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1827 : : tir_attr->rx_hash_toeplitz_key[i]);
1828 : : }
1829 : : outer = MLX5_ADDR_OF(tirc, tir_ctx,
1830 : : rx_hash_field_selector_outer);
1831 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1832 : : tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1833 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1834 : : tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1835 [ # # ]: 0 : MLX5_SET
1836 : : (rx_hash_field_select, outer, selected_fields,
1837 : : tir_attr->rx_hash_field_selector_outer.selected_fields);
1838 : : inner = MLX5_ADDR_OF(tirc, tir_ctx,
1839 : : rx_hash_field_selector_inner);
1840 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1841 : : tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1842 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1843 : : tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1844 [ # # ]: 0 : MLX5_SET
1845 : : (rx_hash_field_select, inner, selected_fields,
1846 : : tir_attr->rx_hash_field_selector_inner.selected_fields);
1847 : : }
1848 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1849 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1850 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1851 : : }
1852 : 0 : ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1853 : : out, sizeof(out));
1854 [ # # ]: 0 : if (ret) {
1855 : 0 : DRV_LOG(ERR, "Failed to modify TIR using DevX");
1856 : 0 : rte_errno = errno;
1857 : 0 : return -errno;
1858 : : }
1859 : : return ret;
1860 : : }
1861 : :
1862 : : /**
1863 : : * Create RQT using DevX API.
1864 : : *
1865 : : * @param[in] ctx
1866 : : * Context returned from mlx5 open_device() glue function.
1867 : : * @param [in] rqt_attr
1868 : : * Pointer to RQT attributes structure.
1869 : : *
1870 : : * @return
1871 : : * The DevX object created, NULL otherwise and rte_errno is set.
1872 : : */
1873 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_rqt)
1874 : : struct mlx5_devx_obj *
1875 : 0 : mlx5_devx_cmd_create_rqt(void *ctx,
1876 : : struct mlx5_devx_rqt_attr *rqt_attr)
1877 : : {
1878 : : uint32_t *in = NULL;
1879 : 0 : uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1880 : 0 : rqt_attr->rqt_actual_size * sizeof(uint32_t);
1881 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1882 : : void *rqt_ctx;
1883 : : struct mlx5_devx_obj *rqt = NULL;
1884 : : unsigned int i;
1885 : :
1886 : 0 : in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1887 [ # # ]: 0 : if (!in) {
1888 : 0 : DRV_LOG(ERR, "Failed to allocate RQT IN data");
1889 : 0 : rte_errno = ENOMEM;
1890 : 0 : return NULL;
1891 : : }
1892 : 0 : rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1893 [ # # ]: 0 : if (!rqt) {
1894 : 0 : DRV_LOG(ERR, "Failed to allocate RQT data");
1895 : 0 : rte_errno = ENOMEM;
1896 : 0 : mlx5_free(in);
1897 : 0 : return NULL;
1898 : : }
1899 [ # # ]: 0 : MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1900 : 0 : rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1901 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1902 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1903 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1904 [ # # ]: 0 : for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1905 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1906 : 0 : rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1907 : 0 : mlx5_free(in);
1908 [ # # ]: 0 : if (!rqt->obj) {
1909 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0);
1910 : 0 : mlx5_free(rqt);
1911 : 0 : return NULL;
1912 : : }
1913 [ # # ]: 0 : rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1914 : 0 : return rqt;
1915 : : }
1916 : :
1917 : : /**
1918 : : * Modify RQT using DevX API.
1919 : : *
1920 : : * @param[in] rqt
1921 : : * Pointer to RQT DevX object structure.
1922 : : * @param [in] rqt_attr
1923 : : * Pointer to RQT attributes structure.
1924 : : *
1925 : : * @return
1926 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
1927 : : */
1928 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_rqt)
1929 : : int
1930 : 0 : mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1931 : : struct mlx5_devx_rqt_attr *rqt_attr)
1932 : : {
1933 : 0 : uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1934 : 0 : rqt_attr->rqt_actual_size * sizeof(uint32_t);
1935 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1936 : 0 : uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1937 : : void *rqt_ctx;
1938 : : unsigned int i;
1939 : : int ret;
1940 : :
1941 [ # # ]: 0 : if (!in) {
1942 : 0 : DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1943 : 0 : rte_errno = ENOMEM;
1944 : 0 : return -ENOMEM;
1945 : : }
1946 [ # # ]: 0 : MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1947 [ # # ]: 0 : MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1948 : 0 : MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1949 : 0 : rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1950 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1951 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1952 [ # # ]: 0 : for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1953 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1954 : 0 : ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1955 : 0 : mlx5_free(in);
1956 [ # # ]: 0 : if (ret) {
1957 : 0 : DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1958 : 0 : rte_errno = errno;
1959 : 0 : return -rte_errno;
1960 : : }
1961 : : return ret;
1962 : : }
1963 : :
1964 : : /**
1965 : : * Create SQ using DevX API.
1966 : : *
1967 : : * @param[in] ctx
1968 : : * Context returned from mlx5 open_device() glue function.
1969 : : * @param [in] sq_attr
1970 : : * Pointer to SQ attributes structure.
1971 : : * @param [in] socket
1972 : : * CPU socket ID for allocations.
1973 : : *
1974 : : * @return
1975 : : * The DevX object created, NULL otherwise and rte_errno is set.
1976 : : **/
1977 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_sq)
1978 : : struct mlx5_devx_obj *
1979 : 0 : mlx5_devx_cmd_create_sq(void *ctx,
1980 : : struct mlx5_devx_create_sq_attr *sq_attr)
1981 : : {
1982 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1983 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1984 : : void *sq_ctx;
1985 : : void *wq_ctx;
1986 : : struct mlx5_devx_wq_attr *wq_attr;
1987 : : struct mlx5_devx_obj *sq = NULL;
1988 : :
1989 : 0 : sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1990 [ # # ]: 0 : if (!sq) {
1991 : 0 : DRV_LOG(ERR, "Failed to allocate SQ data");
1992 : 0 : rte_errno = ENOMEM;
1993 : 0 : return NULL;
1994 : : }
1995 [ # # ]: 0 : MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1996 : : sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1997 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1998 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1999 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
2000 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
2001 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
2002 : : sq_attr->allow_multi_pkt_send_wqe);
2003 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
2004 : : sq_attr->min_wqe_inline_mode);
2005 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
2006 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
2007 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
2008 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
2009 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
2010 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
2011 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type);
2012 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
2013 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
2014 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
2015 : : sq_attr->packet_pacing_rate_limit_index);
2016 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
2017 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
2018 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
2019 : : wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
2020 : 0 : wq_attr = &sq_attr->wq_attr;
2021 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
2022 : 0 : sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2023 : : out, sizeof(out));
2024 [ # # ]: 0 : if (!sq->obj) {
2025 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0);
2026 : 0 : mlx5_free(sq);
2027 : 0 : return NULL;
2028 : : }
2029 [ # # ]: 0 : sq->id = MLX5_GET(create_sq_out, out, sqn);
2030 : 0 : return sq;
2031 : : }
2032 : :
2033 : : /**
2034 : : * Modify SQ using DevX API.
2035 : : *
2036 : : * @param[in] sq
2037 : : * Pointer to SQ object structure.
2038 : : * @param [in] sq_attr
2039 : : * Pointer to SQ attributes structure.
2040 : : *
2041 : : * @return
2042 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2043 : : */
2044 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_sq)
2045 : : int
2046 : 0 : mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
2047 : : struct mlx5_devx_modify_sq_attr *sq_attr)
2048 : : {
2049 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
2050 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
2051 : : void *sq_ctx;
2052 : : int ret;
2053 : :
2054 : 0 : MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
2055 : 0 : MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
2056 [ # # ]: 0 : MLX5_SET(modify_sq_in, in, sqn, sq->id);
2057 : : sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2058 : 0 : MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
2059 : 0 : MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
2060 : 0 : MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
2061 : 0 : ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
2062 : : out, sizeof(out));
2063 [ # # ]: 0 : if (ret) {
2064 : 0 : DRV_LOG(ERR, "Failed to modify SQ using DevX");
2065 : 0 : rte_errno = errno;
2066 : 0 : return -rte_errno;
2067 : : }
2068 : : return ret;
2069 : : }
2070 : :
2071 : : /*
2072 : : * Query SQ using DevX API.
2073 : : *
2074 : : * @param[in] sq_obj
2075 : : * SQ Devx Object
2076 : : * @param[out] out
2077 : : * SQ Query Output
2078 : : * @param[in] outlen
2079 : : * SQ Query Output Length
2080 : : *
2081 : : * @return
2082 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
2083 : : */
2084 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_sq)
2085 : : int
2086 : 0 : mlx5_devx_cmd_query_sq(struct mlx5_devx_obj *sq_obj, void *out, size_t outlen)
2087 : : {
2088 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_sq_in)] = {0};
2089 : : int rc;
2090 : :
2091 : 0 : MLX5_SET(query_sq_in, in, opcode, MLX5_CMD_OP_QUERY_SQ);
2092 : 0 : MLX5_SET(query_sq_in, in, sqn, sq_obj->id);
2093 : 0 : rc = mlx5_glue->devx_obj_query(sq_obj->obj, in, sizeof(in), out, outlen);
2094 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
2095 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "SQ query", "sq_id", sq_obj->id);
2096 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
2097 : : }
2098 : : return 0;
2099 : : }
2100 : :
2101 : : /**
2102 : : * Create TIS using DevX API.
2103 : : *
2104 : : * @param[in] ctx
2105 : : * Context returned from mlx5 open_device() glue function.
2106 : : * @param [in] tis_attr
2107 : : * Pointer to TIS attributes structure.
2108 : : *
2109 : : * @return
2110 : : * The DevX object created, NULL otherwise and rte_errno is set.
2111 : : */
2112 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_tis)
2113 : : struct mlx5_devx_obj *
2114 : 0 : mlx5_devx_cmd_create_tis(void *ctx,
2115 : : struct mlx5_devx_tis_attr *tis_attr)
2116 : : {
2117 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2118 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
2119 : : struct mlx5_devx_obj *tis = NULL;
2120 : : void *tis_ctx;
2121 : :
2122 : 0 : tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
2123 [ # # ]: 0 : if (!tis) {
2124 : 0 : DRV_LOG(ERR, "Failed to allocate TIS object");
2125 : 0 : rte_errno = ENOMEM;
2126 : 0 : return NULL;
2127 : : }
2128 [ # # ]: 0 : MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
2129 : : tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
2130 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
2131 : : tis_attr->strict_lag_tx_port_affinity);
2132 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
2133 : : tis_attr->lag_tx_port_affinity);
2134 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
2135 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, transport_domain,
2136 : : tis_attr->transport_domain);
2137 : 0 : tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2138 : : out, sizeof(out));
2139 [ # # ]: 0 : if (!tis->obj) {
2140 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0);
2141 : 0 : mlx5_free(tis);
2142 : 0 : return NULL;
2143 : : }
2144 [ # # ]: 0 : tis->id = MLX5_GET(create_tis_out, out, tisn);
2145 : 0 : return tis;
2146 : : }
2147 : :
2148 : : /**
2149 : : * Create transport domain using DevX API.
2150 : : *
2151 : : * @param[in] ctx
2152 : : * Context returned from mlx5 open_device() glue function.
2153 : : * @return
2154 : : * The DevX object created, NULL otherwise and rte_errno is set.
2155 : : */
2156 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_td)
2157 : : struct mlx5_devx_obj *
2158 : 0 : mlx5_devx_cmd_create_td(void *ctx)
2159 : : {
2160 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
2161 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
2162 : : struct mlx5_devx_obj *td = NULL;
2163 : :
2164 : 0 : td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
2165 [ # # ]: 0 : if (!td) {
2166 : 0 : DRV_LOG(ERR, "Failed to allocate TD object");
2167 : 0 : rte_errno = ENOMEM;
2168 : 0 : return NULL;
2169 : : }
2170 [ # # ]: 0 : MLX5_SET(alloc_transport_domain_in, in, opcode,
2171 : : MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
2172 : 0 : td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2173 : : out, sizeof(out));
2174 [ # # ]: 0 : if (!td->obj) {
2175 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0);
2176 : 0 : mlx5_free(td);
2177 : 0 : return NULL;
2178 : : }
2179 [ # # ]: 0 : td->id = MLX5_GET(alloc_transport_domain_out, out,
2180 : : transport_domain);
2181 : 0 : return td;
2182 : : }
2183 : :
2184 : : /**
2185 : : * Dump all flows to file.
2186 : : *
2187 : : * @param[in] fdb_domain
2188 : : * FDB domain.
2189 : : * @param[in] rx_domain
2190 : : * RX domain.
2191 : : * @param[in] tx_domain
2192 : : * TX domain.
2193 : : * @param[out] file
2194 : : * Pointer to file stream.
2195 : : *
2196 : : * @return
2197 : : * 0 on success, a negative value otherwise.
2198 : : */
2199 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_dump)
2200 : : int
2201 : 0 : mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
2202 : : void *rx_domain __rte_unused,
2203 : : void *tx_domain __rte_unused, FILE *file __rte_unused)
2204 : : {
2205 : : int ret = 0;
2206 : :
2207 : : #ifdef HAVE_MLX5_DR_FLOW_DUMP
2208 [ # # ]: 0 : if (fdb_domain) {
2209 : 0 : ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
2210 [ # # ]: 0 : if (ret)
2211 : : return ret;
2212 : : }
2213 : : MLX5_ASSERT(rx_domain);
2214 : 0 : ret = mlx5_glue->dr_dump_domain(file, rx_domain);
2215 [ # # ]: 0 : if (ret)
2216 : : return ret;
2217 : : MLX5_ASSERT(tx_domain);
2218 : 0 : ret = mlx5_glue->dr_dump_domain(file, tx_domain);
2219 : : #else
2220 : : ret = ENOTSUP;
2221 : : #endif
2222 : 0 : return -ret;
2223 : : }
2224 : :
2225 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_single_dump)
2226 : : int
2227 : 0 : mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
2228 : : FILE *file __rte_unused)
2229 : : {
2230 : : int ret = 0;
2231 : : #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
2232 [ # # ]: 0 : if (rule_info)
2233 : 0 : ret = mlx5_glue->dr_dump_rule(file, rule_info);
2234 : : #else
2235 : : ret = ENOTSUP;
2236 : : #endif
2237 : 0 : return -ret;
2238 : : }
2239 : :
2240 : : /*
2241 : : * Create CQ using DevX API.
2242 : : *
2243 : : * @param[in] ctx
2244 : : * Context returned from mlx5 open_device() glue function.
2245 : : * @param [in] attr
2246 : : * Pointer to CQ attributes structure.
2247 : : *
2248 : : * @return
2249 : : * The DevX object created, NULL otherwise and rte_errno is set.
2250 : : */
2251 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_cq)
2252 : : struct mlx5_devx_obj *
2253 : 0 : mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
2254 : : {
2255 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
2256 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
2257 : 0 : struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
2258 : : sizeof(*cq_obj),
2259 : : 0, SOCKET_ID_ANY);
2260 : : void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2261 : :
2262 [ # # ]: 0 : if (!cq_obj) {
2263 : 0 : DRV_LOG(ERR, "Failed to allocate CQ object memory.");
2264 : 0 : rte_errno = ENOMEM;
2265 : 0 : return NULL;
2266 : : }
2267 [ # # ]: 0 : MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
2268 [ # # ]: 0 : if (attr->db_umem_valid) {
2269 [ # # ]: 0 : MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
2270 [ # # ]: 0 : MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
2271 [ # # ]: 0 : MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
2272 : : } else {
2273 [ # # ]: 0 : MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
2274 : : }
2275 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
2276 : : MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
2277 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
2278 [ # # ]: 0 : MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
2279 [ # # ]: 0 : MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
2280 [ # # ]: 0 : if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2281 [ # # ]: 0 : MLX5_SET(cqc, cqctx, log_page_size,
2282 : : attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2283 [ # # ]: 0 : MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
2284 [ # # ]: 0 : MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
2285 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
2286 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_comp_layout, !!attr->cqe_comp_layout);
2287 [ # # ]: 0 : MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
2288 [ # # ]: 0 : MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
2289 : : attr->mini_cqe_res_format_ext);
2290 [ # # ]: 0 : if (attr->q_umem_valid) {
2291 [ # # ]: 0 : MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
2292 [ # # ]: 0 : MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
2293 [ # # ]: 0 : MLX5_SET64(create_cq_in, in, cq_umem_offset,
2294 : : attr->q_umem_offset);
2295 : : }
2296 : 0 : cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2297 : : sizeof(out));
2298 [ # # ]: 0 : if (!cq_obj->obj) {
2299 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0);
2300 : 0 : mlx5_free(cq_obj);
2301 : 0 : return NULL;
2302 : : }
2303 [ # # ]: 0 : cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
2304 : 0 : return cq_obj;
2305 : : }
2306 : :
2307 : : /*
2308 : : * Query CQ using DevX API.
2309 : : *
2310 : : * @param[in] cq_obj
2311 : : * CQ Devx Object
2312 : : * @param[out] out
2313 : : * CQ Query Output
2314 : : * @param[in] outlen
2315 : : * CQ Query Output Length
2316 : : *
2317 : : * @return
2318 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
2319 : : */
2320 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_cq)
2321 : : int
2322 : 0 : mlx5_devx_cmd_query_cq(struct mlx5_devx_obj *cq_obj, void *out, size_t outlen)
2323 : : {
2324 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_cq_in)] = {0};
2325 : : int rc;
2326 : :
2327 : 0 : MLX5_SET(query_cq_in, in, opcode, MLX5_CMD_OP_QUERY_CQ);
2328 : 0 : MLX5_SET(query_cq_in, in, cqn, cq_obj->id);
2329 : 0 : rc = mlx5_glue->devx_obj_query(cq_obj->obj, in, sizeof(in), out, outlen);
2330 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
2331 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "CQ query", "cq_id", cq_obj->id);
2332 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
2333 : : }
2334 : : return 0;
2335 : : }
2336 : :
2337 : : /**
2338 : : * Create VIRTQ using DevX API.
2339 : : *
2340 : : * @param[in] ctx
2341 : : * Context returned from mlx5 open_device() glue function.
2342 : : * @param [in] attr
2343 : : * Pointer to VIRTQ attributes structure.
2344 : : *
2345 : : * @return
2346 : : * The DevX object created, NULL otherwise and rte_errno is set.
2347 : : */
2348 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_virtq)
2349 : : struct mlx5_devx_obj *
2350 : 0 : mlx5_devx_cmd_create_virtq(void *ctx,
2351 : : struct mlx5_devx_virtq_attr *attr)
2352 : : {
2353 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
2354 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2355 : 0 : struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
2356 : : sizeof(*virtq_obj),
2357 : : 0, SOCKET_ID_ANY);
2358 : : void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
2359 : : void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
2360 : : void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
2361 : :
2362 [ # # ]: 0 : if (!virtq_obj) {
2363 : 0 : DRV_LOG(ERR, "Failed to allocate virtq data.");
2364 : 0 : rte_errno = ENOMEM;
2365 : 0 : return NULL;
2366 : : }
2367 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2368 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2369 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2370 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2371 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, hw_available_index,
2372 : : attr->hw_available_index);
2373 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
2374 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
2375 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
2376 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
2377 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
2378 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
2379 : : attr->virtio_version_1_0);
2380 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
2381 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
2382 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
2383 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
2384 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
2385 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
2386 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
2387 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
2388 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
2389 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
2390 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
2391 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
2392 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
2393 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
2394 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
2395 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
2396 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
2397 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
2398 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, pd, attr->pd);
2399 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
2400 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
2401 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
2402 [ # # ]: 0 : MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
2403 : 0 : virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2404 : : sizeof(out));
2405 [ # # ]: 0 : if (!virtq_obj->obj) {
2406 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0);
2407 : 0 : mlx5_free(virtq_obj);
2408 : 0 : return NULL;
2409 : : }
2410 [ # # ]: 0 : virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2411 : 0 : return virtq_obj;
2412 : : }
2413 : :
2414 : : /**
2415 : : * Modify VIRTQ using DevX API.
2416 : : *
2417 : : * @param[in] virtq_obj
2418 : : * Pointer to virtq object structure.
2419 : : * @param [in] attr
2420 : : * Pointer to modify virtq attributes structure.
2421 : : *
2422 : : * @return
2423 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2424 : : */
2425 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_virtq)
2426 : : int
2427 : 0 : mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
2428 : : struct mlx5_devx_virtq_attr *attr)
2429 : : {
2430 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
2431 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2432 : : void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
2433 : : void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
2434 : : void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
2435 : : int ret;
2436 : :
2437 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2438 : : MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
2439 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2440 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2441 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2442 [ # # ]: 0 : MLX5_SET64(virtio_net_q, virtq, modify_field_select,
2443 : : attr->mod_fields_bitmap);
2444 : 0 : MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
2445 [ # # ]: 0 : if (!attr->mod_fields_bitmap) {
2446 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ for no type set.");
2447 : 0 : rte_errno = EINVAL;
2448 : 0 : return -rte_errno;
2449 : : }
2450 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE)
2451 : 0 : MLX5_SET16(virtio_net_q, virtq, state, attr->state);
2452 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2453 : : MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) {
2454 : 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
2455 : : attr->dirty_bitmap_mkey);
2456 [ # # ]: 0 : MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
2457 : : attr->dirty_bitmap_addr);
2458 : 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
2459 : : attr->dirty_bitmap_size);
2460 : : }
2461 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2462 : : MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE)
2463 [ # # ]: 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
2464 : : attr->dirty_bitmap_dump_enable);
2465 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) {
2466 : 0 : MLX5_SET(virtio_q, virtctx, queue_period_mode,
2467 : : attr->hw_latency_mode);
2468 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_us,
2469 : : attr->hw_max_latency_us);
2470 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_max_count,
2471 : : attr->hw_max_pending_comp);
2472 : : }
2473 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) {
2474 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
2475 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
2476 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, available_addr,
2477 : : attr->available_addr);
2478 : : }
2479 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX)
2480 : 0 : MLX5_SET16(virtio_net_q, virtq, hw_available_index,
2481 : : attr->hw_available_index);
2482 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX)
2483 : 0 : MLX5_SET16(virtio_net_q, virtq, hw_used_index,
2484 : : attr->hw_used_index);
2485 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE)
2486 : 0 : MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type);
2487 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0)
2488 : 0 : MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
2489 : : attr->virtio_version_1_0);
2490 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY)
2491 : 0 : MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
2492 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2493 : : MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) {
2494 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
2495 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
2496 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
2497 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
2498 : : }
2499 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) {
2500 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
2501 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
2502 : : }
2503 : 0 : ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
2504 : : out, sizeof(out));
2505 [ # # ]: 0 : if (ret) {
2506 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2507 : 0 : rte_errno = errno;
2508 : 0 : return -rte_errno;
2509 : : }
2510 : : return ret;
2511 : : }
2512 : :
2513 : : /**
2514 : : * Query VIRTQ using DevX API.
2515 : : *
2516 : : * @param[in] virtq_obj
2517 : : * Pointer to virtq object structure.
2518 : : * @param [in/out] attr
2519 : : * Pointer to virtq attributes structure.
2520 : : *
2521 : : * @return
2522 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2523 : : */
2524 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_virtq)
2525 : : int
2526 : 0 : mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
2527 : : struct mlx5_devx_virtq_attr *attr)
2528 : : {
2529 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2530 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
2531 : : void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
2532 : : void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
2533 : : int ret;
2534 : :
2535 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2536 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2537 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2538 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2539 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2540 : 0 : ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
2541 : : out, sizeof(out));
2542 [ # # ]: 0 : if (ret) {
2543 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2544 : 0 : rte_errno = errno;
2545 : 0 : return -errno;
2546 : : }
2547 [ # # ]: 0 : attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
2548 : : hw_available_index);
2549 [ # # ]: 0 : attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
2550 [ # # ]: 0 : attr->state = MLX5_GET16(virtio_net_q, virtq, state);
2551 [ # # ]: 0 : attr->error_type = MLX5_GET16(virtio_net_q, virtq,
2552 : : virtio_q_context.error_type);
2553 : 0 : return ret;
2554 : : }
2555 : :
2556 : : /**
2557 : : * Create QP using DevX API.
2558 : : *
2559 : : * @param[in] ctx
2560 : : * Context returned from mlx5 open_device() glue function.
2561 : : * @param [in] attr
2562 : : * Pointer to QP attributes structure.
2563 : : *
2564 : : * @return
2565 : : * The DevX object created, NULL otherwise and rte_errno is set.
2566 : : */
2567 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_qp)
2568 : : struct mlx5_devx_obj *
2569 : 0 : mlx5_devx_cmd_create_qp(void *ctx,
2570 : : struct mlx5_devx_qp_attr *attr)
2571 : : {
2572 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
2573 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
2574 : 0 : struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
2575 : : sizeof(*qp_obj),
2576 : : 0, SOCKET_ID_ANY);
2577 : : void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2578 : :
2579 [ # # ]: 0 : if (!qp_obj) {
2580 : 0 : DRV_LOG(ERR, "Failed to allocate QP data.");
2581 : 0 : rte_errno = ENOMEM;
2582 : 0 : return NULL;
2583 : : }
2584 [ # # ]: 0 : MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
2585 [ # # ]: 0 : MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
2586 [ # # ]: 0 : MLX5_SET(qpc, qpc, pd, attr->pd);
2587 [ # # ]: 0 : MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
2588 [ # # ]: 0 : MLX5_SET(qpc, qpc, user_index, attr->user_index);
2589 [ # # ]: 0 : if (attr->uar_index) {
2590 [ # # ]: 0 : if (attr->mmo) {
2591 : : void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in,
2592 : : in, qpc_extension_and_pas_list);
2593 : : void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list,
2594 : : qpc_ext_and_pas_list, qpc_data_extension);
2595 : :
2596 [ # # ]: 0 : MLX5_SET(create_qp_in, in, qpc_ext, 1);
2597 [ # # ]: 0 : MLX5_SET(qpc_extension, qpc_ext, mmo, 1);
2598 : : }
2599 [ # # ]: 0 : MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2600 [ # # ]: 0 : MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
2601 [ # # ]: 0 : if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2602 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_page_size,
2603 : : attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2604 [ # # ]: 0 : if (attr->num_of_send_wqbbs) {
2605 : : MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs));
2606 [ # # ]: 0 : MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
2607 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_sq_size,
2608 : : rte_log2_u32(attr->num_of_send_wqbbs));
2609 : : } else {
2610 [ # # ]: 0 : MLX5_SET(qpc, qpc, no_sq, 1);
2611 : : }
2612 [ # # ]: 0 : if (attr->num_of_receive_wqes) {
2613 : : MLX5_ASSERT(RTE_IS_POWER_OF_2(
2614 : : attr->num_of_receive_wqes));
2615 [ # # ]: 0 : MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
2616 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
2617 : : MLX5_LOG_RQ_STRIDE_SHIFT);
2618 [ # # # # ]: 0 : MLX5_SET(qpc, qpc, log_rq_size,
2619 : : rte_log2_u32(attr->num_of_receive_wqes));
2620 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
2621 : : } else {
2622 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2623 : : }
2624 [ # # ]: 0 : if (attr->dbr_umem_valid) {
2625 [ # # ]: 0 : MLX5_SET(qpc, qpc, dbr_umem_valid,
2626 : : attr->dbr_umem_valid);
2627 [ # # ]: 0 : MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
2628 : : }
2629 [ # # ]: 0 : if (attr->cd_master)
2630 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_master, attr->cd_master);
2631 [ # # ]: 0 : if (attr->cd_slave_send)
2632 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_slave_send, attr->cd_slave_send);
2633 [ # # ]: 0 : if (attr->cd_slave_recv)
2634 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_slave_receive, attr->cd_slave_recv);
2635 [ # # ]: 0 : MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
2636 [ # # ]: 0 : MLX5_SET64(create_qp_in, in, wq_umem_offset,
2637 : : attr->wq_umem_offset);
2638 [ # # ]: 0 : MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
2639 [ # # ]: 0 : MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
2640 : : } else {
2641 : : /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
2642 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2643 [ # # ]: 0 : MLX5_SET(qpc, qpc, no_sq, 1);
2644 : : }
2645 : 0 : qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2646 : : sizeof(out));
2647 [ # # ]: 0 : if (!qp_obj->obj) {
2648 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0);
2649 : 0 : mlx5_free(qp_obj);
2650 : 0 : return NULL;
2651 : : }
2652 [ # # ]: 0 : qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
2653 : 0 : return qp_obj;
2654 : : }
2655 : :
2656 : : /**
2657 : : * Modify QP using DevX API.
2658 : : * Currently supports only force loop-back QP.
2659 : : *
2660 : : * @param[in] qp
2661 : : * Pointer to QP object structure.
2662 : : * @param [in] qp_st_mod_op
2663 : : * The QP state modification operation.
2664 : : * @param [in] remote_qp_id
2665 : : * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
2666 : : *
2667 : : * @return
2668 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2669 : : */
2670 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_qp_state)
2671 : : int
2672 : 0 : mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
2673 : : uint32_t remote_qp_id)
2674 : : {
2675 : : union {
2676 : : uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
2677 : : uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
2678 : : uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
2679 : : uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)];
2680 : : } in;
2681 : : union {
2682 : : uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
2683 : : uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
2684 : : uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
2685 : : uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)];
2686 : : } out;
2687 : : void *qpc;
2688 : : int ret;
2689 : : unsigned int inlen;
2690 : : unsigned int outlen;
2691 : :
2692 : : memset(&in, 0, sizeof(in));
2693 : : memset(&out, 0, sizeof(out));
2694 : 0 : MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
2695 [ # # # # : 0 : switch (qp_st_mod_op) {
# ]
2696 : 0 : case MLX5_CMD_OP_RST2INIT_QP:
2697 : 0 : MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
2698 : : qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
2699 : 0 : MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2700 : : MLX5_SET(qpc, qpc, rre, 1);
2701 [ # # ]: 0 : MLX5_SET(qpc, qpc, rwe, 1);
2702 : 0 : MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2703 : : inlen = sizeof(in.rst2init);
2704 : : outlen = sizeof(out.rst2init);
2705 : 0 : break;
2706 : 0 : case MLX5_CMD_OP_INIT2RTR_QP:
2707 : 0 : MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2708 : : qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2709 : 0 : MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2710 : 0 : MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2711 : : MLX5_SET(qpc, qpc, mtu, 1);
2712 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_msg_max, 30);
2713 : 0 : MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2714 : 0 : MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2715 : : inlen = sizeof(in.init2rtr);
2716 : : outlen = sizeof(out.init2rtr);
2717 : 0 : break;
2718 : 0 : case MLX5_CMD_OP_RTR2RTS_QP:
2719 : : qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2720 : 0 : MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2721 : 0 : MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16);
2722 : : MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2723 [ # # ]: 0 : MLX5_SET(qpc, qpc, retry_count, 7);
2724 [ # # ]: 0 : MLX5_SET(qpc, qpc, rnr_retry, 7);
2725 : : inlen = sizeof(in.rtr2rts);
2726 : : outlen = sizeof(out.rtr2rts);
2727 : 0 : break;
2728 : 0 : case MLX5_CMD_OP_QP_2RST:
2729 : 0 : MLX5_SET(2rst_qp_in, &in, qpn, qp->id);
2730 : : inlen = sizeof(in.qp2rst);
2731 : : outlen = sizeof(out.qp2rst);
2732 : 0 : break;
2733 : 0 : default:
2734 : 0 : DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2735 : : qp_st_mod_op);
2736 : 0 : rte_errno = EINVAL;
2737 : 0 : return -rte_errno;
2738 : : }
2739 : 0 : ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2740 [ # # ]: 0 : if (ret) {
2741 : 0 : DRV_LOG(ERR, "Failed to modify QP using DevX.");
2742 : 0 : rte_errno = errno;
2743 : 0 : return -rte_errno;
2744 : : }
2745 : : return ret;
2746 : : }
2747 : :
2748 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_virtio_q_counters)
2749 : : struct mlx5_devx_obj *
2750 : 0 : mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2751 : : {
2752 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2753 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2754 : 0 : struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2755 : : sizeof(*couners_obj), 0,
2756 : : SOCKET_ID_ANY);
2757 : : void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2758 : :
2759 [ # # ]: 0 : if (!couners_obj) {
2760 : 0 : DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2761 : 0 : rte_errno = ENOMEM;
2762 : 0 : return NULL;
2763 : : }
2764 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2765 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2766 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2767 : : MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2768 : 0 : couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2769 : : sizeof(out));
2770 [ # # ]: 0 : if (!couners_obj->obj) {
2771 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL,
2772 : : 0);
2773 : 0 : mlx5_free(couners_obj);
2774 : 0 : return NULL;
2775 : : }
2776 [ # # ]: 0 : couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2777 : 0 : return couners_obj;
2778 : : }
2779 : :
2780 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_virtio_q_counters)
2781 : : int
2782 : 0 : mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2783 : : struct mlx5_devx_virtio_q_couners_attr *attr)
2784 : : {
2785 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2786 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2787 : : void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2788 : : void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2789 : : virtio_q_counters);
2790 : : int ret;
2791 : :
2792 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2793 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2794 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2795 : : MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2796 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2797 : 0 : ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2798 : : sizeof(out));
2799 [ # # ]: 0 : if (ret) {
2800 : 0 : DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2801 : 0 : rte_errno = errno;
2802 : 0 : return -errno;
2803 : : }
2804 [ # # ]: 0 : attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2805 : : received_desc);
2806 [ # # ]: 0 : attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2807 : : completed_desc);
2808 [ # # ]: 0 : attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2809 : : error_cqes);
2810 [ # # ]: 0 : attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2811 : : bad_desc_errors);
2812 [ # # ]: 0 : attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2813 : : exceed_max_chain);
2814 [ # # ]: 0 : attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2815 : : invalid_buffer);
2816 : 0 : return ret;
2817 : : }
2818 : :
2819 : : /**
2820 : : * Create general object of type FLOW_HIT_ASO using DevX API.
2821 : : *
2822 : : * @param[in] ctx
2823 : : * Context returned from mlx5 open_device() glue function.
2824 : : * @param [in] pd
2825 : : * PD value to associate the FLOW_HIT_ASO object with.
2826 : : *
2827 : : * @return
2828 : : * The DevX object created, NULL otherwise and rte_errno is set.
2829 : : */
2830 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_flow_hit_aso_obj)
2831 : : struct mlx5_devx_obj *
2832 : 0 : mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2833 : : {
2834 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2835 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2836 : : struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2837 : : void *ptr = NULL;
2838 : :
2839 : 0 : flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2840 : : 0, SOCKET_ID_ANY);
2841 [ # # ]: 0 : if (!flow_hit_aso_obj) {
2842 : 0 : DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2843 : 0 : rte_errno = ENOMEM;
2844 : 0 : return NULL;
2845 : : }
2846 : : ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2847 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2848 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2849 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2850 : : MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2851 : : ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2852 [ # # ]: 0 : MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2853 : 0 : flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2854 : : out, sizeof(out));
2855 [ # # ]: 0 : if (!flow_hit_aso_obj->obj) {
2856 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0);
2857 : 0 : mlx5_free(flow_hit_aso_obj);
2858 : 0 : return NULL;
2859 : : }
2860 [ # # ]: 0 : flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2861 : 0 : return flow_hit_aso_obj;
2862 : : }
2863 : :
2864 : : /*
2865 : : * Create PD using DevX API.
2866 : : *
2867 : : * @param[in] ctx
2868 : : * Context returned from mlx5 open_device() glue function.
2869 : : *
2870 : : * @return
2871 : : * The DevX object created, NULL otherwise and rte_errno is set.
2872 : : */
2873 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_alloc_pd)
2874 : : struct mlx5_devx_obj *
2875 : 0 : mlx5_devx_cmd_alloc_pd(void *ctx)
2876 : : {
2877 : : struct mlx5_devx_obj *ppd =
2878 : 0 : mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2879 : 0 : u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2880 : 0 : u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2881 : :
2882 [ # # ]: 0 : if (!ppd) {
2883 : 0 : DRV_LOG(ERR, "Failed to allocate PD data.");
2884 : 0 : rte_errno = ENOMEM;
2885 : 0 : return NULL;
2886 : : }
2887 : 0 : MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2888 : 0 : ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2889 : : out, sizeof(out));
2890 [ # # ]: 0 : if (!ppd->obj) {
2891 : 0 : mlx5_free(ppd);
2892 : 0 : DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2893 : 0 : rte_errno = errno;
2894 : 0 : return NULL;
2895 : : }
2896 [ # # ]: 0 : ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2897 : 0 : return ppd;
2898 : : }
2899 : :
2900 : : /**
2901 : : * Create general object of type FLOW_METER_ASO using DevX API.
2902 : : *
2903 : : * @param[in] ctx
2904 : : * Context returned from mlx5 open_device() glue function.
2905 : : * @param [in] pd
2906 : : * PD value to associate the FLOW_METER_ASO object with.
2907 : : * @param [in] log_obj_size
2908 : : * log_obj_size define to allocate number of 2 * meters
2909 : : * in one FLOW_METER_ASO object.
2910 : : *
2911 : : * @return
2912 : : * The DevX object created, NULL otherwise and rte_errno is set.
2913 : : */
2914 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_flow_meter_aso_obj)
2915 : : struct mlx5_devx_obj *
2916 : 0 : mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
2917 : : uint32_t log_obj_size)
2918 : : {
2919 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
2920 : : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2921 : : struct mlx5_devx_obj *flow_meter_aso_obj;
2922 : : void *ptr;
2923 : :
2924 : 0 : flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
2925 : : sizeof(*flow_meter_aso_obj),
2926 : : 0, SOCKET_ID_ANY);
2927 [ # # ]: 0 : if (!flow_meter_aso_obj) {
2928 : 0 : DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
2929 : 0 : rte_errno = ENOMEM;
2930 : 0 : return NULL;
2931 : : }
2932 : : ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
2933 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2934 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2935 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2936 : : MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
2937 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
2938 : : log_obj_size);
2939 : : ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
2940 [ # # ]: 0 : MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
2941 : 0 : flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
2942 : : ctx, in, sizeof(in),
2943 : : out, sizeof(out));
2944 [ # # ]: 0 : if (!flow_meter_aso_obj->obj) {
2945 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0);
2946 : 0 : mlx5_free(flow_meter_aso_obj);
2947 : 0 : return NULL;
2948 : : }
2949 [ # # ]: 0 : flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
2950 : : out, obj_id);
2951 : 0 : return flow_meter_aso_obj;
2952 : : }
2953 : :
2954 : : /*
2955 : : * Create general object of type CONN_TRACK_OFFLOAD using DevX API.
2956 : : *
2957 : : * @param[in] ctx
2958 : : * Context returned from mlx5 open_device() glue function.
2959 : : * @param [in] pd
2960 : : * PD value to associate the CONN_TRACK_OFFLOAD ASO object with.
2961 : : * @param [in] log_obj_size
2962 : : * log_obj_size to allocate its power of 2 * objects
2963 : : * in one CONN_TRACK_OFFLOAD bulk allocation.
2964 : : *
2965 : : * @return
2966 : : * The DevX object created, NULL otherwise and rte_errno is set.
2967 : : */
2968 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_conn_track_offload_obj)
2969 : : struct mlx5_devx_obj *
2970 : 0 : mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd,
2971 : : uint32_t log_obj_size)
2972 : : {
2973 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0};
2974 : : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2975 : : struct mlx5_devx_obj *ct_aso_obj;
2976 : : void *ptr;
2977 : :
2978 : 0 : ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj),
2979 : : 0, SOCKET_ID_ANY);
2980 [ # # ]: 0 : if (!ct_aso_obj) {
2981 : 0 : DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object.");
2982 : 0 : rte_errno = ENOMEM;
2983 : 0 : return NULL;
2984 : : }
2985 : : ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr);
2986 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2987 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2988 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2989 : : MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD);
2990 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size);
2991 : : ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload);
2992 [ # # ]: 0 : MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd);
2993 : 0 : ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2994 : : out, sizeof(out));
2995 [ # # ]: 0 : if (!ct_aso_obj->obj) {
2996 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0);
2997 : 0 : mlx5_free(ct_aso_obj);
2998 : 0 : return NULL;
2999 : : }
3000 [ # # ]: 0 : ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3001 : 0 : return ct_aso_obj;
3002 : : }
3003 : :
3004 : : /**
3005 : : * Create general object of type GENEVE TLV option using DevX API.
3006 : : *
3007 : : * @param[in] ctx
3008 : : * Context returned from mlx5 open_device() glue function.
3009 : : * @param[in] attr
3010 : : * Pointer to GENEVE TLV option attributes structure.
3011 : : *
3012 : : * @return
3013 : : * The DevX object created, NULL otherwise and rte_errno is set.
3014 : : */
3015 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_geneve_tlv_option)
3016 : : struct mlx5_devx_obj *
3017 : 0 : mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
3018 : : struct mlx5_devx_geneve_tlv_option_attr *attr)
3019 : : {
3020 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
3021 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3022 : 0 : struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
3023 : : sizeof(*geneve_tlv_opt_obj),
3024 : : 0, SOCKET_ID_ANY);
3025 : :
3026 [ # # ]: 0 : if (!geneve_tlv_opt_obj) {
3027 : 0 : DRV_LOG(ERR, "Failed to allocate GENEVE TLV option object.");
3028 : 0 : rte_errno = ENOMEM;
3029 : 0 : return NULL;
3030 : : }
3031 : : void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
3032 : : void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
3033 : : geneve_tlv_opt);
3034 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
3035 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3036 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
3037 : : MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
3038 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_type, attr->option_type);
3039 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_data_length,
3040 : : attr->option_data_len);
3041 [ # # ]: 0 : if (attr->option_class_ignore)
3042 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_class_ignore,
3043 : : attr->option_class_ignore);
3044 : : else
3045 [ # # # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_class,
3046 : : rte_be_to_cpu_16(attr->option_class));
3047 [ # # ]: 0 : if (attr->offset_valid) {
3048 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, sample_offset_valid,
3049 : : attr->offset_valid);
3050 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, sample_offset,
3051 : : attr->sample_offset);
3052 : : }
3053 : 0 : geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
3054 : : sizeof(in), out,
3055 : : sizeof(out));
3056 [ # # ]: 0 : if (!geneve_tlv_opt_obj->obj) {
3057 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create GENEVE TLV option", NULL, 0);
3058 : 0 : mlx5_free(geneve_tlv_opt_obj);
3059 : 0 : return NULL;
3060 : : }
3061 [ # # ]: 0 : geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3062 : 0 : return geneve_tlv_opt_obj;
3063 : : }
3064 : :
3065 : : /**
3066 : : * Query GENEVE TLV option using DevX API.
3067 : : *
3068 : : * @param[in] ctx
3069 : : * Context used to create GENEVE TLV option object.
3070 : : * @param[in] geneve_tlv_opt_obj
3071 : : * DevX object of the GENEVE TLV option.
3072 : : * @param[out] attr
3073 : : * Pointer to match sample info attributes structure.
3074 : : *
3075 : : * @return
3076 : : * 0 on success, a negative errno otherwise and rte_errno is set.
3077 : : */
3078 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_geneve_tlv_option)
3079 : : int
3080 : 0 : mlx5_devx_cmd_query_geneve_tlv_option(void *ctx,
3081 : : struct mlx5_devx_obj *geneve_tlv_opt_obj,
3082 : : struct mlx5_devx_match_sample_info_query_attr *attr)
3083 : : {
3084 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
3085 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_geneve_tlv_option_out)] = {0};
3086 : : void *hdr = MLX5_ADDR_OF(query_geneve_tlv_option_out, in, hdr);
3087 : : void *opt = MLX5_ADDR_OF(query_geneve_tlv_option_out, out,
3088 : : geneve_tlv_opt);
3089 : : int ret;
3090 : :
3091 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
3092 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
3093 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
3094 : : MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
3095 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, geneve_tlv_opt_obj->id);
3096 : : /* Call first query to get sample handle. */
3097 : 0 : ret = mlx5_glue->devx_obj_query(geneve_tlv_opt_obj->obj, in, sizeof(in),
3098 : : out, sizeof(out));
3099 [ # # ]: 0 : if (ret) {
3100 : 0 : DRV_LOG(ERR, "Failed to query GENEVE TLV option using DevX.");
3101 : 0 : rte_errno = errno;
3102 : 0 : return -errno;
3103 : : }
3104 : : /* Call second query to get sample information. */
3105 [ # # # # ]: 0 : if (MLX5_GET(geneve_tlv_option, opt, sample_id_valid)) {
3106 [ # # ]: 0 : uint32_t sample_id = MLX5_GET(geneve_tlv_option, opt,
3107 : : geneve_sample_field_id);
3108 : :
3109 : 0 : return mlx5_devx_cmd_match_sample_info_query(ctx, sample_id,
3110 : : attr);
3111 : : }
3112 : 0 : DRV_LOG(DEBUG, "GENEVE TLV option sample isn't valid.");
3113 : 0 : return 0;
3114 : : }
3115 : :
3116 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_wq_query)
3117 : : int
3118 : 0 : mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
3119 : : {
3120 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3121 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
3122 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
3123 : : int rc;
3124 : : void *rq_ctx;
3125 : :
3126 : 0 : MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
3127 : 0 : MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
3128 : 0 : rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
3129 [ # # ]: 0 : if (rc) {
3130 : 0 : rte_errno = errno;
3131 : 0 : DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
3132 : : "rc = %d, errno = %d.", rc, errno);
3133 : 0 : return -rc;
3134 : : };
3135 : : rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
3136 [ # # ]: 0 : *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
3137 : 0 : return 0;
3138 : : #else
3139 : : (void)wq;
3140 : : (void)counter_set_id;
3141 : : return -ENOTSUP;
3142 : : #endif
3143 : : }
3144 : :
3145 : : /*
3146 : : * Allocate queue counters via devx interface.
3147 : : *
3148 : : * @param[in] ctx
3149 : : * Context returned from mlx5 open_device() glue function.
3150 : : * @param[out] syndrome
3151 : : * Get syndrome of devx command response.
3152 : : *
3153 : : * @return
3154 : : * Pointer to counter object on success, a NULL value otherwise and
3155 : : * rte_errno is set.
3156 : : */
3157 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_queue_counter_alloc)
3158 : : struct mlx5_devx_obj *
3159 : 0 : mlx5_devx_cmd_queue_counter_alloc(void *ctx, int *syndrome)
3160 : : {
3161 : : int status;
3162 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
3163 : : SOCKET_ID_ANY);
3164 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0};
3165 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
3166 : :
3167 [ # # ]: 0 : if (!dcs) {
3168 : 0 : rte_errno = ENOMEM;
3169 : 0 : return NULL;
3170 : : }
3171 : 0 : MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
3172 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
3173 : : sizeof(out));
3174 [ # # ]: 0 : if (!dcs->obj) {
3175 [ # # # # ]: 0 : DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0);
3176 [ # # ]: 0 : status = MLX5_GET(alloc_q_counter_out, out, status);
3177 [ # # ]: 0 : if (status && syndrome)
3178 [ # # ]: 0 : *syndrome = MLX5_GET(alloc_q_counter_out, out, syndrome);
3179 : 0 : mlx5_free(dcs);
3180 : 0 : return NULL;
3181 : : }
3182 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
3183 : 0 : return dcs;
3184 : : }
3185 : :
3186 : : /**
3187 : : * Query queue counters values.
3188 : : *
3189 : : * @param[in] dcs
3190 : : * devx object of the queue counter set.
3191 : : * @param[in] clear
3192 : : * Whether hardware should clear the counters after the query or not.
3193 : : * @param[out] out_of_buffers
3194 : : * Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
3195 : : *
3196 : : * @return
3197 : : * 0 on success, a negative value otherwise.
3198 : : */
3199 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_queue_counter_query)
3200 : : int
3201 : 0 : mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
3202 : : uint32_t *out_of_buffers)
3203 : : {
3204 : 0 : uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
3205 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
3206 : : int rc;
3207 : :
3208 : 0 : MLX5_SET(query_q_counter_in, in, opcode,
3209 : : MLX5_CMD_OP_QUERY_Q_COUNTER);
3210 : 0 : MLX5_SET(query_q_counter_in, in, op_mod, 0);
3211 : 0 : MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
3212 : 0 : MLX5_SET(query_q_counter_in, in, clear, !!clear);
3213 : 0 : rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
3214 : : sizeof(out));
3215 [ # # ]: 0 : if (rc) {
3216 : 0 : DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
3217 : 0 : rte_errno = rc;
3218 : 0 : return -rc;
3219 : : }
3220 [ # # ]: 0 : *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
3221 : 0 : return 0;
3222 : : }
3223 : :
3224 : : /**
3225 : : * Create general object of type DEK using DevX API.
3226 : : *
3227 : : * @param[in] ctx
3228 : : * Context returned from mlx5 open_device() glue function.
3229 : : * @param [in] attr
3230 : : * Pointer to DEK attributes structure.
3231 : : *
3232 : : * @return
3233 : : * The DevX object created, NULL otherwise and rte_errno is set.
3234 : : */
3235 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_dek_obj)
3236 : : struct mlx5_devx_obj *
3237 : 0 : mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)
3238 : : {
3239 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};
3240 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3241 : : struct mlx5_devx_obj *dek_obj = NULL;
3242 : : void *ptr = NULL, *key_addr = NULL;
3243 : :
3244 : 0 : dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),
3245 : : 0, SOCKET_ID_ANY);
3246 [ # # ]: 0 : if (dek_obj == NULL) {
3247 : 0 : DRV_LOG(ERR, "Failed to allocate DEK object data");
3248 : 0 : rte_errno = ENOMEM;
3249 : 0 : return NULL;
3250 : : }
3251 : : ptr = MLX5_ADDR_OF(create_dek_in, in, hdr);
3252 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3253 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3254 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3255 : : MLX5_GENERAL_OBJ_TYPE_DEK);
3256 : : ptr = MLX5_ADDR_OF(create_dek_in, in, dek);
3257 [ # # ]: 0 : MLX5_SET(dek, ptr, key_size, attr->key_size);
3258 [ # # ]: 0 : MLX5_SET(dek, ptr, has_keytag, attr->has_keytag);
3259 [ # # ]: 0 : MLX5_SET(dek, ptr, key_purpose, attr->key_purpose);
3260 [ # # ]: 0 : MLX5_SET(dek, ptr, pd, attr->pd);
3261 [ # # ]: 0 : MLX5_SET64(dek, ptr, opaque, attr->opaque);
3262 : : key_addr = MLX5_ADDR_OF(dek, ptr, key);
3263 : 0 : memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
3264 : 0 : dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3265 : : out, sizeof(out));
3266 [ # # ]: 0 : if (dek_obj->obj == NULL) {
3267 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0);
3268 : 0 : mlx5_free(dek_obj);
3269 : 0 : return NULL;
3270 : : }
3271 [ # # ]: 0 : dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3272 : 0 : return dek_obj;
3273 : : }
3274 : :
3275 : : /**
3276 : : * Create general object of type IMPORT_KEK using DevX API.
3277 : : *
3278 : : * @param[in] ctx
3279 : : * Context returned from mlx5 open_device() glue function.
3280 : : * @param [in] attr
3281 : : * Pointer to IMPORT_KEK attributes structure.
3282 : : *
3283 : : * @return
3284 : : * The DevX object created, NULL otherwise and rte_errno is set.
3285 : : */
3286 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_import_kek_obj)
3287 : : struct mlx5_devx_obj *
3288 : 0 : mlx5_devx_cmd_create_import_kek_obj(void *ctx,
3289 : : struct mlx5_devx_import_kek_attr *attr)
3290 : : {
3291 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0};
3292 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3293 : : struct mlx5_devx_obj *import_kek_obj = NULL;
3294 : : void *ptr = NULL, *key_addr = NULL;
3295 : :
3296 : 0 : import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj),
3297 : : 0, SOCKET_ID_ANY);
3298 [ # # ]: 0 : if (import_kek_obj == NULL) {
3299 : 0 : DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data");
3300 : 0 : rte_errno = ENOMEM;
3301 : 0 : return NULL;
3302 : : }
3303 : : ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr);
3304 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3305 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3306 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3307 : : MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK);
3308 : : ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek);
3309 [ # # ]: 0 : MLX5_SET(import_kek, ptr, key_size, attr->key_size);
3310 : : key_addr = MLX5_ADDR_OF(import_kek, ptr, key);
3311 : 0 : memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
3312 : 0 : import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3313 : : out, sizeof(out));
3314 [ # # ]: 0 : if (import_kek_obj->obj == NULL) {
3315 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0);
3316 : 0 : mlx5_free(import_kek_obj);
3317 : 0 : return NULL;
3318 : : }
3319 [ # # ]: 0 : import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3320 : 0 : return import_kek_obj;
3321 : : }
3322 : :
3323 : : /**
3324 : : * Create general object of type CREDENTIAL using DevX API.
3325 : : *
3326 : : * @param[in] ctx
3327 : : * Context returned from mlx5 open_device() glue function.
3328 : : * @param [in] attr
3329 : : * Pointer to CREDENTIAL attributes structure.
3330 : : *
3331 : : * @return
3332 : : * The DevX object created, NULL otherwise and rte_errno is set.
3333 : : */
3334 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_credential_obj)
3335 : : struct mlx5_devx_obj *
3336 : 0 : mlx5_devx_cmd_create_credential_obj(void *ctx,
3337 : : struct mlx5_devx_credential_attr *attr)
3338 : : {
3339 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0};
3340 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3341 : : struct mlx5_devx_obj *credential_obj = NULL;
3342 : : void *ptr = NULL, *credential_addr = NULL;
3343 : :
3344 : 0 : credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj),
3345 : : 0, SOCKET_ID_ANY);
3346 [ # # ]: 0 : if (credential_obj == NULL) {
3347 : 0 : DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data");
3348 : 0 : rte_errno = ENOMEM;
3349 : 0 : return NULL;
3350 : : }
3351 : : ptr = MLX5_ADDR_OF(create_credential_in, in, hdr);
3352 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3353 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3354 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3355 : : MLX5_GENERAL_OBJ_TYPE_CREDENTIAL);
3356 : : ptr = MLX5_ADDR_OF(create_credential_in, in, credential);
3357 [ # # ]: 0 : MLX5_SET(credential, ptr, credential_role, attr->credential_role);
3358 : : credential_addr = MLX5_ADDR_OF(credential, ptr, credential);
3359 : 0 : memcpy(credential_addr, (void *)(attr->credential),
3360 : : MLX5_CRYPTO_CREDENTIAL_SIZE);
3361 : 0 : credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3362 : : out, sizeof(out));
3363 [ # # ]: 0 : if (credential_obj->obj == NULL) {
3364 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0);
3365 : 0 : mlx5_free(credential_obj);
3366 : 0 : return NULL;
3367 : : }
3368 [ # # ]: 0 : credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3369 : 0 : return credential_obj;
3370 : : }
3371 : :
3372 : : /**
3373 : : * Create general object of type CRYPTO_LOGIN using DevX API.
3374 : : *
3375 : : * @param[in] ctx
3376 : : * Context returned from mlx5 open_device() glue function.
3377 : : * @param [in] attr
3378 : : * Pointer to CRYPTO_LOGIN attributes structure.
3379 : : *
3380 : : * @return
3381 : : * The DevX object created, NULL otherwise and rte_errno is set.
3382 : : */
3383 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_crypto_login_obj)
3384 : : struct mlx5_devx_obj *
3385 : 0 : mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
3386 : : struct mlx5_devx_crypto_login_attr *attr)
3387 : : {
3388 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0};
3389 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3390 : : struct mlx5_devx_obj *crypto_login_obj = NULL;
3391 : : void *ptr = NULL, *credential_addr = NULL;
3392 : :
3393 : 0 : crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj),
3394 : : 0, SOCKET_ID_ANY);
3395 [ # # ]: 0 : if (crypto_login_obj == NULL) {
3396 : 0 : DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data");
3397 : 0 : rte_errno = ENOMEM;
3398 : 0 : return NULL;
3399 : : }
3400 : : ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr);
3401 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3402 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3403 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3404 : : MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN);
3405 : : ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login);
3406 [ # # ]: 0 : MLX5_SET(crypto_login, ptr, credential_pointer,
3407 : : attr->credential_pointer);
3408 [ # # ]: 0 : MLX5_SET(crypto_login, ptr, session_import_kek_ptr,
3409 : : attr->session_import_kek_ptr);
3410 : : credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential);
3411 : 0 : memcpy(credential_addr, (void *)(attr->credential),
3412 : : MLX5_CRYPTO_CREDENTIAL_SIZE);
3413 : 0 : crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3414 : : out, sizeof(out));
3415 [ # # ]: 0 : if (crypto_login_obj->obj == NULL) {
3416 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0);
3417 : 0 : mlx5_free(crypto_login_obj);
3418 : 0 : return NULL;
3419 : : }
3420 [ # # ]: 0 : crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3421 : 0 : return crypto_login_obj;
3422 : : }
3423 : :
3424 : : /**
3425 : : * Query LAG context.
3426 : : *
3427 : : * @param[in] ctx
3428 : : * Pointer to ibv_context, returned from mlx5dv_open_device.
3429 : : * @param[out] lag_ctx
3430 : : * Pointer to struct mlx5_devx_lag_context, to be set by the routine.
3431 : : *
3432 : : * @return
3433 : : * 0 on success, a negative value otherwise.
3434 : : */
3435 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_lag)
3436 : : int
3437 : 0 : mlx5_devx_cmd_query_lag(void *ctx,
3438 : : struct mlx5_devx_lag_context *lag_ctx)
3439 : : {
3440 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0};
3441 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0};
3442 : : void *lctx;
3443 : : int rc;
3444 : :
3445 : 0 : MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG);
3446 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
3447 [ # # ]: 0 : if (rc)
3448 : 0 : goto error;
3449 : : lctx = MLX5_ADDR_OF(query_lag_out, out, context);
3450 [ # # ]: 0 : lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx,
3451 : : fdb_selection_mode);
3452 [ # # ]: 0 : lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx,
3453 : : port_select_mode);
3454 [ # # ]: 0 : lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state);
3455 [ # # ]: 0 : lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx,
3456 : : tx_remap_affinity_2);
3457 [ # # ]: 0 : lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx,
3458 : : tx_remap_affinity_1);
3459 : 0 : return 0;
3460 : : error:
3461 : 0 : rc = (rc > 0) ? -rc : rc;
3462 : 0 : return rc;
3463 : : }
|
