Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright 2018 Mellanox Technologies, Ltd
3 : : */
4 : :
5 : : #include <unistd.h>
6 : :
7 : : #include <eal_export.h>
8 : : #include <rte_errno.h>
9 : : #include <rte_malloc.h>
10 : : #include <rte_eal_paging.h>
11 : :
12 : : #include "mlx5_prm.h"
13 : : #include "mlx5_devx_cmds.h"
14 : : #include "mlx5_common_log.h"
15 : : #include "mlx5_malloc.h"
16 : :
17 : : /* FW writes status value to the OUT buffer at offset 00H */
18 : : #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status)
19 : : /* FW writes syndrome value to the OUT buffer at offset 04H */
20 : : #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome)
21 : :
22 : : #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1))
23 : :
24 : : #define DEVX_DRV_LOG(level, out, reason, param, value) \
25 : : do { \
26 : : /* \
27 : : * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \
28 : : * do not expand correctly when the macro invoked when the `param` \
29 : : * is `NULL`. \
30 : : * Use `local_param` to avoid direct `NULL` expansion. \
31 : : */ \
32 : : const char *local_param = (const char *)param; \
33 : : \
34 : : rte_errno = errno; \
35 : : if (!local_param) { \
36 : : DRV_LOG(level, \
37 : : "DevX %s failed errno=%d status=%#x syndrome=%#x", \
38 : : (reason), errno, MLX5_FW_STATUS((out)), \
39 : : MLX5_FW_SYNDROME((out))); \
40 : : } else { \
41 : : DRV_LOG(level, \
42 : : "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\
43 : : (reason), local_param, (value), errno, \
44 : : MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \
45 : : } \
46 : : } while (0)
47 : :
48 : : static void *
49 [ # # ]: 0 : mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out,
50 : : int *err, uint32_t flags)
51 : : {
52 : : const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int);
53 : : const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int);
54 : : int rc;
55 : :
56 : : memset(in, 0, size_in);
57 : : memset(out, 0, size_out);
58 [ # # ]: 0 : MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
59 [ # # ]: 0 : MLX5_SET(query_hca_cap_in, in, op_mod, flags);
60 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out);
61 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
62 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1);
63 [ # # ]: 0 : if (err)
64 [ # # ]: 0 : *err = MLX5_DEVX_ERR_RC(rc);
65 : 0 : return NULL;
66 : : }
67 [ # # ]: 0 : if (err)
68 : 0 : *err = 0;
69 : 0 : return MLX5_ADDR_OF(query_hca_cap_out, out, capability);
70 : : }
71 : :
72 : : /**
73 : : * Perform read access to the registers. Reads data from register
74 : : * and writes ones to the specified buffer.
75 : : *
76 : : * @param[in] ctx
77 : : * Context returned from mlx5 open_device() glue function.
78 : : * @param[in] reg_id
79 : : * Register identifier according to the PRM.
80 : : * @param[in] arg
81 : : * Register access auxiliary parameter according to the PRM.
82 : : * @param[out] data
83 : : * Pointer to the buffer to store read data.
84 : : * @param[in] dw_cnt
85 : : * Buffer size in double words.
86 : : *
87 : : * @return
88 : : * 0 on success, a negative value otherwise.
89 : : */
90 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_register_read)
91 : : int
92 : 0 : mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
93 : : uint32_t *data, uint32_t dw_cnt)
94 : : {
95 : 0 : uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0};
96 : 0 : uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
97 : : MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
98 : : int rc;
99 : :
100 : : MLX5_ASSERT(data && dw_cnt);
101 : : MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
102 [ # # ]: 0 : if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
103 : 0 : DRV_LOG(ERR, "Not enough buffer for register read data");
104 : 0 : return -1;
105 : : }
106 : 0 : MLX5_SET(access_register_in, in, opcode,
107 : : MLX5_CMD_OP_ACCESS_REGISTER_USER);
108 : 0 : MLX5_SET(access_register_in, in, op_mod,
109 : : MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
110 : 0 : MLX5_SET(access_register_in, in, register_id, reg_id);
111 : 0 : MLX5_SET(access_register_in, in, argument, arg);
112 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
113 : 0 : MLX5_ST_SZ_BYTES(access_register_out) +
114 : : sizeof(uint32_t) * dw_cnt);
115 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
116 [ # # # # ]: 0 : DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id);
117 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
118 : : }
119 : 0 : memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
120 : : dw_cnt * sizeof(uint32_t));
121 : 0 : return 0;
122 : : }
123 : :
124 : : /**
125 : : * Perform write access to the registers.
126 : : *
127 : : * @param[in] ctx
128 : : * Context returned from mlx5 open_device() glue function.
129 : : * @param[in] reg_id
130 : : * Register identifier according to the PRM.
131 : : * @param[in] arg
132 : : * Register access auxiliary parameter according to the PRM.
133 : : * @param[out] data
134 : : * Pointer to the buffer containing data to write.
135 : : * @param[in] dw_cnt
136 : : * Buffer size in double words (32bit units).
137 : : *
138 : : * @return
139 : : * 0 on success, a negative value otherwise.
140 : : */
141 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_register_write)
142 : : int
143 : 0 : mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg,
144 : : uint32_t *data, uint32_t dw_cnt)
145 : : {
146 : 0 : uint32_t in[MLX5_ST_SZ_DW(access_register_in) +
147 : : MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
148 : 0 : uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0};
149 : : int rc;
150 : : void *ptr;
151 : :
152 : : MLX5_ASSERT(data && dw_cnt);
153 : : MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
154 [ # # ]: 0 : if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
155 : 0 : DRV_LOG(ERR, "Data to write exceeds max size");
156 : 0 : return -1;
157 : : }
158 : 0 : MLX5_SET(access_register_in, in, opcode,
159 : : MLX5_CMD_OP_ACCESS_REGISTER_USER);
160 : 0 : MLX5_SET(access_register_in, in, op_mod,
161 : : MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE);
162 : 0 : MLX5_SET(access_register_in, in, register_id, reg_id);
163 : 0 : MLX5_SET(access_register_in, in, argument, arg);
164 : : ptr = MLX5_ADDR_OF(access_register_in, in, register_data);
165 : 0 : memcpy(ptr, data, dw_cnt * sizeof(uint32_t));
166 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
167 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
168 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id);
169 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
170 : : }
171 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in,
172 : 0 : MLX5_ST_SZ_BYTES(access_register_in) +
173 : : dw_cnt * sizeof(uint32_t),
174 : : out, sizeof(out));
175 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
176 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id);
177 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
178 : : }
179 : : return 0;
180 : : }
181 : :
182 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_counter_alloc_general)
183 : : struct mlx5_devx_obj *
184 : 0 : mlx5_devx_cmd_flow_counter_alloc_general(void *ctx,
185 : : struct mlx5_devx_counter_attr *attr)
186 : : {
187 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
188 : : 0, SOCKET_ID_ANY);
189 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
190 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
191 : :
192 [ # # ]: 0 : if (!dcs) {
193 : 0 : rte_errno = ENOMEM;
194 : 0 : return NULL;
195 : : }
196 : 0 : MLX5_SET(alloc_flow_counter_in, in, opcode,
197 : : MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
198 [ # # ]: 0 : if (attr->bulk_log_max_alloc)
199 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk_log_size,
200 : : attr->flow_counter_bulk_log_size);
201 : : else
202 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk,
203 : : attr->bulk_n_128);
204 [ # # ]: 0 : if (attr->pd_valid)
205 : 0 : MLX5_SET(alloc_flow_counter_in, in, pd, attr->pd);
206 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
207 : : sizeof(in), out, sizeof(out));
208 [ # # ]: 0 : if (!dcs->obj) {
209 : 0 : DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
210 : 0 : rte_errno = errno;
211 : 0 : mlx5_free(dcs);
212 : 0 : return NULL;
213 : : }
214 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
215 : 0 : return dcs;
216 : : }
217 : :
218 : : /**
219 : : * Allocate flow counters via devx interface.
220 : : *
221 : : * @param[in] ctx
222 : : * Context returned from mlx5 open_device() glue function.
223 : : * @param dcs
224 : : * Pointer to counters properties structure to be filled by the routine.
225 : : * @param bulk_n_128
226 : : * Bulk counter numbers in 128 counters units.
227 : : *
228 : : * @return
229 : : * Pointer to counter object on success, a negative value otherwise and
230 : : * rte_errno is set.
231 : : */
232 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_counter_alloc)
233 : : struct mlx5_devx_obj *
234 : 0 : mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
235 : : {
236 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
237 : : 0, SOCKET_ID_ANY);
238 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
239 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
240 : :
241 [ # # ]: 0 : if (!dcs) {
242 : 0 : rte_errno = ENOMEM;
243 : 0 : return NULL;
244 : : }
245 : 0 : MLX5_SET(alloc_flow_counter_in, in, opcode,
246 : : MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
247 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
248 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
249 : : sizeof(in), out, sizeof(out));
250 [ # # ]: 0 : if (!dcs->obj) {
251 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0);
252 : 0 : mlx5_free(dcs);
253 : 0 : return NULL;
254 : : }
255 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
256 : 0 : return dcs;
257 : : }
258 : :
259 : : /**
260 : : * Query flow counters values.
261 : : *
262 : : * @param[in] dcs
263 : : * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
264 : : * @param[in] clear
265 : : * Whether hardware should clear the counters after the query or not.
266 : : * @param[in] n_counters
267 : : * 0 in case of 1 counter to read, otherwise the counter number to read.
268 : : * @param pkts
269 : : * The number of packets that matched the flow.
270 : : * @param bytes
271 : : * The number of bytes that matched the flow.
272 : : * @param mkey
273 : : * The mkey key for batch query.
274 : : * @param addr
275 : : * The address in the mkey range for batch query.
276 : : * @param cmd_comp
277 : : * The completion object for asynchronous batch query.
278 : : * @param async_id
279 : : * The ID to be returned in the asynchronous batch query response.
280 : : *
281 : : * @return
282 : : * 0 on success, a negative value otherwise.
283 : : */
284 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_counter_query)
285 : : int
286 : 0 : mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
287 : : int clear, uint32_t n_counters,
288 : : uint64_t *pkts, uint64_t *bytes,
289 : : uint32_t mkey, void *addr,
290 : : void *cmd_comp,
291 : : uint64_t async_id)
292 : : {
293 : : uint32_t out[MLX5_ST_SZ_BYTES(query_flow_counter_out) + MLX5_ST_SZ_BYTES(traffic_counter)];
294 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
295 : : const int out_len = RTE_DIM(out);
296 : : void *stats;
297 : : int rc;
298 : :
299 : 0 : MLX5_SET(query_flow_counter_in, in, opcode,
300 : : MLX5_CMD_OP_QUERY_FLOW_COUNTER);
301 : 0 : MLX5_SET(query_flow_counter_in, in, op_mod, 0);
302 : 0 : MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
303 : 0 : MLX5_SET(query_flow_counter_in, in, clear, !!clear);
304 : :
305 [ # # ]: 0 : if (n_counters) {
306 [ # # ]: 0 : MLX5_SET(query_flow_counter_in, in, num_of_counters,
307 : : n_counters);
308 [ # # ]: 0 : MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
309 : 0 : MLX5_SET(query_flow_counter_in, in, mkey, mkey);
310 : 0 : MLX5_SET64(query_flow_counter_in, in, address,
311 : : (uint64_t)(uintptr_t)addr);
312 : : }
313 [ # # ]: 0 : if (!cmd_comp)
314 : 0 : rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
315 : : out_len);
316 : : else
317 : 0 : rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
318 : : out_len, async_id,
319 : : cmd_comp);
320 [ # # ]: 0 : if (rc) {
321 : 0 : DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
322 : 0 : rte_errno = rc;
323 : 0 : return -rc;
324 : : }
325 [ # # ]: 0 : if (!n_counters) {
326 : : stats = MLX5_ADDR_OF(query_flow_counter_out,
327 : : out, flow_statistics);
328 [ # # ]: 0 : *pkts = MLX5_GET64(traffic_counter, stats, packets);
329 [ # # ]: 0 : *bytes = MLX5_GET64(traffic_counter, stats, octets);
330 : : }
331 : : return 0;
332 : : }
333 : :
334 : : /**
335 : : * Create a new mkey.
336 : : *
337 : : * @param[in] ctx
338 : : * Context returned from mlx5 open_device() glue function.
339 : : * @param[in] attr
340 : : * Attributes of the requested mkey.
341 : : *
342 : : * @return
343 : : * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
344 : : * is set.
345 : : */
346 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_mkey_create)
347 : : struct mlx5_devx_obj *
348 : 0 : mlx5_devx_cmd_mkey_create(void *ctx,
349 : : struct mlx5_devx_mkey_attr *attr)
350 : : {
351 : 0 : struct mlx5_klm *klm_array = attr->klm_array;
352 : 0 : int klm_num = attr->klm_num;
353 [ # # ]: 0 : int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
354 : 0 : (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
355 : 0 : uint32_t *in = alloca(sizeof(uint32_t) * in_size_dw);
356 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
357 : : void *mkc;
358 : 0 : struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
359 : : 0, SOCKET_ID_ANY);
360 : : size_t pgsize;
361 : : uint32_t translation_size;
362 : :
363 [ # # ]: 0 : if (!mkey) {
364 : 0 : rte_errno = ENOMEM;
365 : 0 : return NULL;
366 : : }
367 : : memset(in, 0, in_size_dw * 4);
368 : 0 : pgsize = rte_mem_page_size();
369 [ # # ]: 0 : if (pgsize == (size_t)-1) {
370 : 0 : mlx5_free(mkey);
371 : 0 : DRV_LOG(ERR, "Failed to get page size");
372 : 0 : rte_errno = ENOMEM;
373 : 0 : return NULL;
374 : : }
375 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
376 : : mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
377 [ # # ]: 0 : if (klm_num > 0) {
378 : : int i;
379 : 0 : uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
380 : : klm_pas_mtt);
381 : 0 : translation_size = RTE_ALIGN(klm_num, 4);
382 [ # # ]: 0 : for (i = 0; i < klm_num; i++) {
383 [ # # ]: 0 : MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
384 [ # # ]: 0 : MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
385 [ # # ]: 0 : MLX5_SET64(klm, klm, address, klm_array[i].address);
386 : 0 : klm += MLX5_ST_SZ_BYTES(klm);
387 : : }
388 [ # # ]: 0 : for (; i < (int)translation_size; i++) {
389 [ # # ]: 0 : MLX5_SET(klm, klm, mkey, 0x0);
390 : 0 : MLX5_SET64(klm, klm, address, 0x0);
391 : 0 : klm += MLX5_ST_SZ_BYTES(klm);
392 : : }
393 [ # # # # ]: 0 : MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
394 : : MLX5_MKC_ACCESS_MODE_KLM_FBS :
395 : : MLX5_MKC_ACCESS_MODE_KLM);
396 [ # # ]: 0 : MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
397 : : } else {
398 : 0 : translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
399 [ # # ]: 0 : MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
400 [ # # # # ]: 0 : MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
401 : : }
402 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
403 : : translation_size);
404 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
405 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
406 [ # # ]: 0 : MLX5_SET(mkc, mkc, lw, 0x1);
407 [ # # ]: 0 : MLX5_SET(mkc, mkc, lr, 0x1);
408 [ # # ]: 0 : if (attr->set_remote_rw) {
409 [ # # ]: 0 : MLX5_SET(mkc, mkc, rw, 0x1);
410 [ # # ]: 0 : MLX5_SET(mkc, mkc, rr, 0x1);
411 : : }
412 [ # # ]: 0 : MLX5_SET(mkc, mkc, qpn, 0xffffff);
413 [ # # ]: 0 : MLX5_SET(mkc, mkc, pd, attr->pd);
414 [ # # ]: 0 : MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
415 [ # # ]: 0 : MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
416 [ # # ]: 0 : MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
417 [ # # ]: 0 : MLX5_SET(mkc, mkc, relaxed_ordering_write,
418 : : attr->relaxed_ordering_write);
419 [ # # ]: 0 : MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
420 [ # # ]: 0 : MLX5_SET64(mkc, mkc, start_addr, attr->addr);
421 [ # # ]: 0 : MLX5_SET64(mkc, mkc, len, attr->size);
422 [ # # ]: 0 : MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en);
423 [ # # ]: 0 : if (attr->crypto_en) {
424 [ # # ]: 0 : MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en);
425 [ # # ]: 0 : MLX5_SET(mkc, mkc, bsf_octword_size, 4);
426 : : }
427 : 0 : mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
428 : : sizeof(out));
429 [ # # ]: 0 : if (!mkey->obj) {
430 [ # # # # : 0 : DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey"
# # ]
431 : : : "create direct key", NULL, 0);
432 : 0 : mlx5_free(mkey);
433 : 0 : return NULL;
434 : : }
435 [ # # ]: 0 : mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
436 : 0 : mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
437 : 0 : return mkey;
438 : : }
439 : :
440 : : /**
441 : : * Get status of devx command response.
442 : : * Mainly used for asynchronous commands.
443 : : *
444 : : * @param[in] out
445 : : * The out response buffer.
446 : : *
447 : : * @return
448 : : * 0 on success, non-zero value otherwise.
449 : : */
450 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_get_out_command_status)
451 : : int
452 : 0 : mlx5_devx_get_out_command_status(void *out)
453 : : {
454 : : int status;
455 : :
456 [ # # ]: 0 : if (!out)
457 : : return -EINVAL;
458 [ # # ]: 0 : status = MLX5_GET(query_flow_counter_out, out, status);
459 [ # # ]: 0 : if (status) {
460 [ # # ]: 0 : int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
461 : :
462 : 0 : DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
463 : : syndrome);
464 : : }
465 : : return status;
466 : : }
467 : :
468 : : /**
469 : : * Destroy any object allocated by a Devx API.
470 : : *
471 : : * @param[in] obj
472 : : * Pointer to a general object.
473 : : *
474 : : * @return
475 : : * 0 on success, a negative value otherwise.
476 : : */
477 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_destroy)
478 : : int
479 : 0 : mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
480 : : {
481 : : int ret;
482 : :
483 [ # # ]: 0 : if (!obj)
484 : : return 0;
485 : 0 : ret = mlx5_glue->devx_obj_destroy(obj->obj);
486 : 0 : mlx5_free(obj);
487 : 0 : return ret;
488 : : }
489 : :
490 : : static int
491 : 0 : mlx5_devx_cmd_query_esw_vport_context(void *ctx,
492 : : struct mlx5_hca_attr *attr)
493 : : {
494 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {0};
495 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {0};
496 : : void *vctx;
497 : : int rc;
498 : :
499 : 0 : MLX5_SET(query_esw_vport_context_in, in, opcode, MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
500 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
501 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
502 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "query ESW vport context", NULL, 0);
503 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
504 : : }
505 : : vctx = MLX5_ADDR_OF(query_esw_vport_context_out, out, esw_vport_context);
506 [ # # ]: 0 : attr->fdb_to_vport_reg_c = MLX5_GET(esw_vport_context, vctx, fdb_to_vport_reg_c);
507 [ # # ]: 0 : if (attr->fdb_to_vport_reg_c != 0) {
508 : 0 : attr->vport_to_fdb_metadata =
509 [ # # ]: 0 : MLX5_GET(esw_vport_context, vctx, vport_to_fdb_metadata);
510 : 0 : attr->fdb_to_vport_metadata =
511 [ # # ]: 0 : MLX5_GET(esw_vport_context, vctx, fdb_to_vport_metadata);
512 [ # # ]: 0 : attr->fdb_to_vport_reg_c_id =
513 : 0 : MLX5_GET(esw_vport_context, vctx, fdb_to_vport_reg_c_id);
514 : : }
515 : : return 0;
516 : : }
517 : :
518 : : /**
519 : : * Query NIC vport context.
520 : : * Fills minimal inline attribute.
521 : : *
522 : : * @param[in] ctx
523 : : * ibv contexts returned from mlx5dv_open_device.
524 : : * @param[in] vport
525 : : * vport index
526 : : * @param[out] attr
527 : : * Attributes device values.
528 : : *
529 : : * @return
530 : : * 0 on success, a negative value otherwise.
531 : : */
532 : : static int
533 : 0 : mlx5_devx_cmd_query_nic_vport_context(void *ctx,
534 : : unsigned int vport,
535 : : struct mlx5_hca_attr *attr)
536 : : {
537 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
538 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
539 : : void *vctx;
540 : : int rc;
541 : :
542 : : /* Query NIC vport context to determine inline mode. */
543 : 0 : MLX5_SET(query_nic_vport_context_in, in, opcode,
544 : : MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
545 : 0 : MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
546 [ # # ]: 0 : if (vport)
547 [ # # ]: 0 : MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
548 : 0 : rc = mlx5_glue->devx_general_cmd(ctx,
549 : : in, sizeof(in),
550 : : out, sizeof(out));
551 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
552 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0);
553 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
554 : : }
555 : : vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
556 : : nic_vport_context);
557 [ # # ]: 0 : if (attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
558 [ # # ]: 0 : attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
559 : : min_wqe_inline_mode);
560 [ # # ]: 0 : attr->system_image_guid = MLX5_GET64(nic_vport_context, vctx,
561 : : system_image_guid);
562 [ # # ]: 0 : attr->vport_to_fdb_metadata = MLX5_GET(nic_vport_context, vctx, vport_to_fdb_metadata);
563 [ # # ]: 0 : attr->fdb_to_vport_metadata = MLX5_GET(nic_vport_context, vctx, fdb_to_vport_metadata);
564 : 0 : return 0;
565 : : }
566 : :
567 : : /**
568 : : * Query NIC vDPA attributes.
569 : : *
570 : : * @param[in] ctx
571 : : * Context returned from mlx5 open_device() glue function.
572 : : * @param[out] vdpa_attr
573 : : * vDPA Attributes structure to fill.
574 : : */
575 : : static void
576 : 0 : mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
577 : : struct mlx5_hca_vdpa_attr *vdpa_attr)
578 : : {
579 : : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
580 : : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
581 : : void *hcattr;
582 : :
583 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL,
584 : : MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
585 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
586 [ # # ]: 0 : if (!hcattr) {
587 : 0 : DRV_LOG(DEBUG, "Failed to query devx VDPA capabilities");
588 : 0 : vdpa_attr->valid = 0;
589 : : } else {
590 : 0 : vdpa_attr->valid = 1;
591 : 0 : vdpa_attr->desc_tunnel_offload_type =
592 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
593 : : desc_tunnel_offload_type);
594 : 0 : vdpa_attr->eth_frame_offload_type =
595 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
596 : : eth_frame_offload_type);
597 : 0 : vdpa_attr->virtio_version_1_0 =
598 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
599 : : virtio_version_1_0);
600 [ # # ]: 0 : vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
601 : : tso_ipv4);
602 [ # # ]: 0 : vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
603 : : tso_ipv6);
604 [ # # ]: 0 : vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
605 : : tx_csum);
606 [ # # ]: 0 : vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
607 : : rx_csum);
608 [ # # ]: 0 : vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
609 : : event_mode);
610 : 0 : vdpa_attr->virtio_queue_type =
611 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
612 : : virtio_queue_type);
613 : 0 : vdpa_attr->log_doorbell_stride =
614 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
615 : : log_doorbell_stride);
616 : 0 : vdpa_attr->vnet_modify_ext =
617 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
618 : : vnet_modify_ext);
619 : 0 : vdpa_attr->virtio_net_q_addr_modify =
620 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
621 : : virtio_net_q_addr_modify);
622 : 0 : vdpa_attr->virtio_q_index_modify =
623 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
624 : : virtio_q_index_modify);
625 : 0 : vdpa_attr->log_doorbell_bar_size =
626 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
627 : : log_doorbell_bar_size);
628 : 0 : vdpa_attr->doorbell_bar_offset =
629 [ # # ]: 0 : MLX5_GET64(virtio_emulation_cap, hcattr,
630 : : doorbell_bar_offset);
631 : 0 : vdpa_attr->max_num_virtio_queues =
632 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
633 : : max_num_virtio_queues);
634 [ # # ]: 0 : vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
635 : : umem_1_buffer_param_a);
636 [ # # ]: 0 : vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
637 : : umem_1_buffer_param_b);
638 [ # # ]: 0 : vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
639 : : umem_2_buffer_param_a);
640 [ # # ]: 0 : vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
641 : : umem_2_buffer_param_b);
642 [ # # ]: 0 : vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
643 : : umem_3_buffer_param_a);
644 [ # # ]: 0 : vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
645 : : umem_3_buffer_param_b);
646 : : }
647 : 0 : }
648 : :
649 : : /**
650 : : * Query match sample handle parameters.
651 : : *
652 : : * This command allows translating a field sample handle returned by either
653 : : * PARSE_GRAPH_FLOW_MATCH_SAMPLE or by GENEVE TLV OPTION object into values
654 : : * used for header modification or header matching/hashing.
655 : : *
656 : : * @param[in] ctx
657 : : * Context used to create either GENEVE TLV option or FLEX PARSE GRAPH object.
658 : : * @param[in] sample_field_id
659 : : * Field sample handle returned by either PARSE_GRAPH_FLOW_MATCH_SAMPLE
660 : : * or by GENEVE TLV OPTION object.
661 : : * @param[out] attr
662 : : * Pointer to match sample info attributes structure.
663 : : *
664 : : * @return
665 : : * 0 on success, a negative errno otherwise and rte_errno is set.
666 : : */
667 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_match_sample_info_query)
668 : : int
669 : 0 : mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id,
670 : : struct mlx5_devx_match_sample_info_query_attr *attr)
671 : : {
672 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
673 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_match_sample_info_out)] = {0};
674 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_match_sample_info_in)] = {0};
675 : : int rc;
676 : :
677 : 0 : MLX5_SET(query_match_sample_info_in, in, opcode,
678 : : MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO);
679 : 0 : MLX5_SET(query_match_sample_info_in, in, op_mod, 0);
680 : 0 : MLX5_SET(query_match_sample_info_in, in, sample_field_id,
681 : : sample_field_id);
682 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
683 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
684 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "query match sample info",
685 : : "sample_field_id", sample_field_id);
686 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
687 : : }
688 [ # # ]: 0 : attr->modify_field_id = MLX5_GET(query_match_sample_info_out, out,
689 : : modify_field_id);
690 [ # # ]: 0 : attr->sample_dw_data = MLX5_GET(query_match_sample_info_out, out,
691 : : field_format_select_dw);
692 [ # # ]: 0 : attr->sample_dw_ok_bit = MLX5_GET(query_match_sample_info_out, out,
693 : : ok_bit_format_select_dw);
694 [ # # ]: 0 : attr->sample_dw_ok_bit_offset = MLX5_GET(query_match_sample_info_out,
695 : : out, ok_bit_offset);
696 : 0 : return 0;
697 : : #else
698 : : (void)ctx;
699 : : (void)sample_field_id;
700 : : (void)attr;
701 : : return -ENOTSUP;
702 : : #endif
703 : : }
704 : :
705 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_parse_samples)
706 : : int
707 : 0 : mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
708 : : uint32_t *ids,
709 : : uint32_t num, uint8_t *anchor)
710 : : {
711 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
712 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
713 : : void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
714 : : void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
715 : : void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
716 : : int ret;
717 : : uint32_t idx = 0;
718 : : uint32_t i;
719 : :
720 [ # # ]: 0 : if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
721 : 0 : rte_errno = EINVAL;
722 : 0 : DRV_LOG(ERR, "Too many sample IDs to be fetched.");
723 : 0 : return -rte_errno;
724 : : }
725 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
726 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
727 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
728 : : MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
729 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
730 : 0 : ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
731 : : out, sizeof(out));
732 [ # # ]: 0 : if (ret) {
733 : 0 : rte_errno = ret;
734 : 0 : DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
735 : : (void *)flex_obj);
736 : 0 : return -rte_errno;
737 : : }
738 [ # # ]: 0 : if (anchor)
739 [ # # ]: 0 : *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id);
740 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx < num; i++) {
741 : 0 : void *s_off = (void *)((char *)sample + i *
742 : : MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
743 : : uint32_t en;
744 : :
745 [ # # ]: 0 : en = MLX5_GET(parse_graph_flow_match_sample, s_off,
746 : : flow_match_sample_en);
747 [ # # ]: 0 : if (!en)
748 : 0 : continue;
749 [ # # ]: 0 : ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
750 : : flow_match_sample_field_id);
751 : : }
752 [ # # ]: 0 : if (num != idx) {
753 : 0 : rte_errno = EINVAL;
754 : 0 : DRV_LOG(ERR, "Number of sample IDs are not as expected.");
755 : 0 : return -rte_errno;
756 : : }
757 : : return ret;
758 : : }
759 : :
760 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_flex_parser)
761 : : struct mlx5_devx_obj *
762 : 0 : mlx5_devx_cmd_create_flex_parser(void *ctx,
763 : : struct mlx5_devx_graph_node_attr *data)
764 : : {
765 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
766 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
767 : : void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
768 : : void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
769 : : void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
770 : : void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
771 : : void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
772 : 0 : struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
773 : : (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
774 : : uint32_t i;
775 : :
776 [ # # ]: 0 : if (!parse_flex_obj) {
777 : 0 : DRV_LOG(ERR, "Failed to allocate flex parser data.");
778 : 0 : rte_errno = ENOMEM;
779 : 0 : return NULL;
780 : : }
781 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
782 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
783 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
784 : : MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
785 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_mode,
786 : : data->header_length_mode);
787 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_offset_mode,
788 : : data->header_length_field_offset_mode);
789 [ # # ]: 0 : MLX5_SET64(parse_graph_flex, flex, modify_field_select,
790 : : data->modify_field_select);
791 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_base_value,
792 : : data->header_length_base_value);
793 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
794 : : data->header_length_field_offset);
795 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
796 : : data->header_length_field_shift);
797 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, next_header_field_offset,
798 : : data->next_header_field_offset);
799 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, next_header_field_size,
800 : : data->next_header_field_size);
801 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
802 : : data->header_length_field_mask);
803 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
804 : : struct mlx5_devx_match_sample_attr *s = &data->sample[i];
805 : 0 : void *s_off = (void *)((char *)sample + i *
806 : : MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
807 : :
808 [ # # ]: 0 : if (!s->flow_match_sample_en)
809 : 0 : continue;
810 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
811 : : flow_match_sample_en, !!s->flow_match_sample_en);
812 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
813 : : flow_match_sample_field_offset,
814 : : s->flow_match_sample_field_offset);
815 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
816 : : flow_match_sample_offset_mode,
817 : : s->flow_match_sample_offset_mode);
818 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
819 : : flow_match_sample_field_offset_mask,
820 : : s->flow_match_sample_field_offset_mask);
821 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
822 : : flow_match_sample_field_offset_shift,
823 : : s->flow_match_sample_field_offset_shift);
824 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
825 : : flow_match_sample_field_base_offset,
826 : : s->flow_match_sample_field_base_offset);
827 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
828 : : flow_match_sample_tunnel_mode,
829 : : s->flow_match_sample_tunnel_mode);
830 : : }
831 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
832 : : struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
833 : : struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
834 : 0 : void *in_off = (void *)((char *)in_arc + i *
835 : : MLX5_ST_SZ_BYTES(parse_graph_arc));
836 : 0 : void *out_off = (void *)((char *)out_arc + i *
837 : : MLX5_ST_SZ_BYTES(parse_graph_arc));
838 : :
839 [ # # ]: 0 : if (ia->arc_parse_graph_node != 0) {
840 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off,
841 : : compare_condition_value,
842 : : ia->compare_condition_value);
843 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
844 : : ia->start_inner_tunnel);
845 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
846 : : ia->arc_parse_graph_node);
847 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off,
848 : : parse_graph_node_handle,
849 : : ia->parse_graph_node_handle);
850 : : }
851 [ # # ]: 0 : if (oa->arc_parse_graph_node != 0) {
852 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off,
853 : : compare_condition_value,
854 : : oa->compare_condition_value);
855 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
856 : : oa->start_inner_tunnel);
857 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
858 : : oa->arc_parse_graph_node);
859 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off,
860 : : parse_graph_node_handle,
861 : : oa->parse_graph_node_handle);
862 : : }
863 : : }
864 : 0 : parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
865 : : out, sizeof(out));
866 [ # # ]: 0 : if (!parse_flex_obj->obj) {
867 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0);
868 : 0 : mlx5_free(parse_flex_obj);
869 : 0 : return NULL;
870 : : }
871 [ # # ]: 0 : parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
872 : 0 : return parse_flex_obj;
873 : : }
874 : :
875 : : static int
876 : 0 : mlx5_devx_cmd_query_hca_parse_graph_node_cap
877 : : (void *ctx, struct mlx5_hca_flex_attr *attr)
878 : : {
879 : : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
880 : : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
881 : : void *hcattr;
882 : : int rc;
883 : :
884 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
885 : : MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP |
886 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
887 [ # # ]: 0 : if (!hcattr)
888 : 0 : return rc;
889 [ # # ]: 0 : attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in);
890 [ # # ]: 0 : attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out);
891 [ # # ]: 0 : attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr,
892 : : header_length_mode);
893 [ # # ]: 0 : attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr,
894 : : sample_offset_mode);
895 [ # # ]: 0 : attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr,
896 : : max_num_arc_in);
897 [ # # ]: 0 : attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr,
898 : : max_num_arc_out);
899 [ # # ]: 0 : attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr,
900 : : max_num_sample);
901 [ # # ]: 0 : attr->parse_graph_anchor = MLX5_GET(parse_graph_node_cap, hcattr, parse_graph_anchor);
902 [ # # ]: 0 : attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr,
903 : : sample_tunnel_inner2);
904 [ # # ]: 0 : attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr,
905 : : zero_size_supported);
906 [ # # ]: 0 : attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr,
907 : : sample_id_in_out);
908 [ # # ]: 0 : attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr,
909 : : max_base_header_length);
910 [ # # ]: 0 : attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr,
911 : : max_sample_base_offset);
912 [ # # ]: 0 : attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr,
913 : : max_next_header_offset);
914 [ # # ]: 0 : attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr,
915 : : header_length_mask_width);
916 [ # # ]: 0 : attr->header_length_field_mode_wa = !MLX5_GET(parse_graph_node_cap, hcattr,
917 : : header_length_field_offset_mode);
918 : : /* Get the max supported samples from HCA CAP 2 */
919 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
920 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
921 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
922 [ # # ]: 0 : if (!hcattr)
923 : 0 : return rc;
924 : 0 : attr->max_num_prog_sample =
925 [ # # ]: 0 : MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field);
926 : 0 : return 0;
927 : : }
928 : :
929 : : static int
930 : 0 : mlx5_devx_query_pkt_integrity_match(void *hcattr)
931 : : {
932 [ # # ]: 0 : return MLX5_GET(flow_table_nic_cap, hcattr,
933 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l3_ok) &&
934 : : MLX5_GET(flow_table_nic_cap, hcattr,
935 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l4_ok) &&
936 : : MLX5_GET(flow_table_nic_cap, hcattr,
937 [ # # # # ]: 0 : ft_field_support_2_nic_receive.outer_l3_ok) &&
938 : : MLX5_GET(flow_table_nic_cap, hcattr,
939 [ # # # # ]: 0 : ft_field_support_2_nic_receive.outer_l4_ok) &&
940 : : MLX5_GET(flow_table_nic_cap, hcattr,
941 : : ft_field_support_2_nic_receive
942 [ # # # # ]: 0 : .inner_ipv4_checksum_ok) &&
943 : : MLX5_GET(flow_table_nic_cap, hcattr,
944 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l4_checksum_ok) &&
945 : : MLX5_GET(flow_table_nic_cap, hcattr,
946 : : ft_field_support_2_nic_receive
947 [ # # # # : 0 : .outer_ipv4_checksum_ok) &&
# # # # #
# # # # #
# # # # ]
948 [ # # # # ]: 0 : MLX5_GET(flow_table_nic_cap, hcattr,
949 : : ft_field_support_2_nic_receive.outer_l4_checksum_ok);
950 : : }
951 : :
952 : : /**
953 : : * Query HCA attributes.
954 : : * Using those attributes we can check on run time if the device
955 : : * is having the required capabilities.
956 : : *
957 : : * @param[in] ctx
958 : : * Context returned from mlx5 open_device() glue function.
959 : : * @param[out] attr
960 : : * Attributes device values.
961 : : *
962 : : * @return
963 : : * 0 on success, a negative value otherwise.
964 : : */
965 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_hca_attr)
966 : : int
967 : 0 : mlx5_devx_cmd_query_hca_attr(void *ctx,
968 : : struct mlx5_hca_attr *attr)
969 : : {
970 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
971 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
972 : : bool hca_cap_2_sup;
973 : : uint64_t general_obj_types_supported = 0;
974 : : uint64_t stc_action_type_127_64;
975 : : void *hcattr;
976 : : int rc, i;
977 : :
978 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
979 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
980 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
981 [ # # ]: 0 : if (!hcattr)
982 : 0 : return rc;
983 [ # # ]: 0 : hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2);
984 [ # # ]: 0 : attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq);
985 : 0 : attr->flow_counter_bulk_alloc_bitmap =
986 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
987 [ # # ]: 0 : attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
988 : : flow_counters_dump);
989 [ # # ]: 0 : attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp);
990 [ # # ]: 0 : attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp);
991 [ # # ]: 0 : attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
992 : : log_max_rqt_size);
993 [ # # ]: 0 : attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
994 [ # # ]: 0 : attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
995 [ # # ]: 0 : attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
996 : : log_max_hairpin_queues);
997 [ # # ]: 0 : attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
998 : : log_max_hairpin_wq_data_sz);
999 [ # # ]: 0 : attr->log_max_hairpin_num_packets = MLX5_GET
1000 : : (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
1001 [ # # ]: 0 : attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
1002 [ # # ]: 0 : attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
1003 : : relaxed_ordering_write);
1004 [ # # ]: 0 : attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
1005 : : relaxed_ordering_read);
1006 [ # # ]: 0 : attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
1007 : : access_register_user);
1008 [ # # ]: 0 : attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
1009 : : eth_net_offloads);
1010 [ # # ]: 0 : attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
1011 [ # # ]: 0 : attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
1012 : : flex_parser_protocols);
1013 [ # # ]: 0 : attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
1014 : : max_geneve_tlv_options);
1015 [ # # ]: 0 : attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
1016 : : max_geneve_tlv_option_data_len);
1017 [ # # ]: 0 : attr->geneve_tlv_option_offset = MLX5_GET(cmd_hca_cap, hcattr,
1018 : : geneve_tlv_option_offset);
1019 [ # # ]: 0 : attr->geneve_tlv_sample = MLX5_GET(cmd_hca_cap, hcattr,
1020 : : geneve_tlv_sample);
1021 [ # # ]: 0 : attr->query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr,
1022 : : query_match_sample_info);
1023 [ # # ]: 0 : attr->geneve_tlv_option_sample_id = MLX5_GET(cmd_hca_cap, hcattr,
1024 : : flex_parser_id_geneve_opt_0);
1025 [ # # ]: 0 : attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
1026 [ # # ]: 0 : attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
1027 : : wqe_index_ignore_cap);
1028 [ # # ]: 0 : attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
1029 [ # # ]: 0 : attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
1030 [ # # ]: 0 : attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
1031 : : log_max_static_sq_wq);
1032 [ # # ]: 0 : attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
1033 [ # # ]: 0 : attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
1034 : : device_frequency_khz);
1035 : 0 : attr->scatter_fcs_w_decap_disable =
1036 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
1037 [ # # ]: 0 : attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
1038 [ # # ]: 0 : attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
1039 [ # # ]: 0 : attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
1040 : 0 : attr->steering_format_version =
1041 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, steering_format_version);
1042 [ # # ]: 0 : attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params);
1043 [ # # ]: 0 : attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version);
1044 [ # # ]: 0 : attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
1045 : : regexp_num_of_engines);
1046 : : /* Read the general_obj_types bitmap and extract the relevant bits. */
1047 [ # # ]: 0 : general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
1048 : : general_obj_types);
1049 : 0 : attr->qos.flow_meter_aso_sup =
1050 : 0 : !!(general_obj_types_supported &
1051 : : MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
1052 : 0 : attr->vdpa.valid = !!(general_obj_types_supported &
1053 : : MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
1054 : 0 : attr->vdpa.queue_counters_valid =
1055 : 0 : !!(general_obj_types_supported &
1056 : : MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
1057 : 0 : attr->parse_graph_flex_node =
1058 : 0 : !!(general_obj_types_supported &
1059 : : MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
1060 : 0 : attr->flow_hit_aso = !!(general_obj_types_supported &
1061 : : MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
1062 : 0 : attr->geneve_tlv_opt = !!(general_obj_types_supported &
1063 : : MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
1064 : 0 : attr->dek = !!(general_obj_types_supported &
1065 : : MLX5_GENERAL_OBJ_TYPES_CAP_DEK);
1066 : 0 : attr->import_kek = !!(general_obj_types_supported &
1067 : : MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK);
1068 : 0 : attr->credential = !!(general_obj_types_supported &
1069 : : MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL);
1070 : 0 : attr->crypto_login = !!(general_obj_types_supported &
1071 : : MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN);
1072 : : /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
1073 [ # # ]: 0 : attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
1074 [ # # ]: 0 : attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
1075 [ # # ]: 0 : attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
1076 [ # # ]: 0 : attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
1077 [ # # ]: 0 : attr->log_max_wq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_wq_sz);
1078 [ # # ]: 0 : attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
1079 [ # # ]: 0 : attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
1080 [ # # ]: 0 : attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
1081 [ # # ]: 0 : attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
1082 : 0 : attr->reg_c_preserve =
1083 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
1084 [ # # ]: 0 : attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp);
1085 [ # # ]: 0 : attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq);
1086 [ # # ]: 0 : attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq);
1087 [ # # ]: 0 : attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
1088 : : compress_mmo_sq);
1089 [ # # ]: 0 : attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
1090 : : decompress_mmo_sq);
1091 [ # # ]: 0 : attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp);
1092 [ # # ]: 0 : attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,
1093 : : compress_mmo_qp);
1094 [ # # ]: 0 : attr->decomp_deflate_v1_en = MLX5_GET(cmd_hca_cap, hcattr,
1095 : : decompress_deflate_v1);
1096 [ # # ]: 0 : attr->decomp_deflate_v2_en = MLX5_GET(cmd_hca_cap, hcattr,
1097 : : decompress_deflate_v2);
1098 [ # # ]: 0 : attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
1099 : : compress_min_block_size);
1100 [ # # ]: 0 : attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
1101 [ # # ]: 0 : attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
1102 : : log_compress_mmo_size);
1103 [ # # ]: 0 : attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
1104 : : log_decompress_mmo_size);
1105 [ # # ]: 0 : attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr,
1106 : : decompress_lz4_data_only_v2);
1107 [ # # ]: 0 : attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr,
1108 : : decompress_lz4_no_checksum_v2);
1109 [ # # ]: 0 : attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr,
1110 : : decompress_lz4_checksum_v2);
1111 [ # # ]: 0 : attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
1112 [ # # ]: 0 : attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
1113 : : mini_cqe_resp_flow_tag);
1114 [ # # ]: 0 : attr->cqe_compression_128 = MLX5_GET(cmd_hca_cap, hcattr,
1115 : : cqe_compression_128);
1116 [ # # ]: 0 : attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
1117 : : mini_cqe_resp_l3_l4_tag);
1118 [ # # ]: 0 : attr->enhanced_cqe_compression = MLX5_GET(cmd_hca_cap, hcattr,
1119 : : enhanced_cqe_compression);
1120 : 0 : attr->umr_indirect_mkey_disabled =
1121 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
1122 : 0 : attr->umr_modify_entity_size_disabled =
1123 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
1124 [ # # ]: 0 : attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time);
1125 [ # # ]: 0 : attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
1126 : 0 : attr->ct_offload = !!(general_obj_types_supported &
1127 : : MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);
1128 [ # # ]: 0 : attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop);
1129 [ # # ]: 0 : attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table);
1130 [ # # ]: 0 : attr->striding_rq = MLX5_GET(cmd_hca_cap, hcattr, striding_rq);
1131 : 0 : attr->ext_stride_num_range =
1132 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, ext_stride_num_range);
1133 [ # # ]: 0 : attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table);
1134 [ # # ]: 0 : attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr,
1135 : : max_flow_counter_15_0);
1136 [ # # ]: 0 : attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr,
1137 : : max_flow_counter_31_16);
1138 [ # # ]: 0 : attr->alloc_flow_counter_pd = MLX5_GET(cmd_hca_cap, hcattr,
1139 : : alloc_flow_counter_pd);
1140 [ # # ]: 0 : attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr,
1141 : : flow_counter_access_aso);
1142 [ # # ]: 0 : attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr,
1143 : : flow_access_aso_opc_mod);
1144 [ # # ]: 0 : attr->wqe_based_flow_table_sup = MLX5_GET(cmd_hca_cap, hcattr,
1145 : : wqe_based_flow_table_update_cap);
1146 : : /*
1147 : : * Flex item support needs max_num_prog_sample_field
1148 : : * from the Capabilities 2 table for PARSE_GRAPH_NODE
1149 : : */
1150 [ # # ]: 0 : if (attr->parse_graph_flex_node) {
1151 : 0 : rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap
1152 : : (ctx, &attr->flex);
1153 [ # # ]: 0 : if (rc)
1154 : : return -1;
1155 : 0 : attr->flex.query_match_sample_info =
1156 : 0 : attr->query_match_sample_info;
1157 : : }
1158 [ # # ]: 0 : if (attr->crypto) {
1159 [ # # # # : 0 : attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) ||
# # ]
1160 [ # # # # : 0 : MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) ||
# # # # #
# # # ]
1161 : : MLX5_GET(cmd_hca_cap, hcattr, aes_xts_single_block_le_tweak);
1162 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1163 : : MLX5_GET_HCA_CAP_OP_MOD_CRYPTO |
1164 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1165 [ # # ]: 0 : if (!hcattr)
1166 : : return -1;
1167 [ # # ]: 0 : attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps,
1168 : : hcattr, wrapped_import_method)
1169 : 0 : & 1 << 2);
1170 [ # # ]: 0 : attr->crypto_mmo.crypto_mmo_qp = MLX5_GET(crypto_caps, hcattr, crypto_mmo_qp);
1171 : 0 : attr->crypto_mmo.gcm_256_encrypt =
1172 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_encrypt);
1173 : 0 : attr->crypto_mmo.gcm_128_encrypt =
1174 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_encrypt);
1175 : 0 : attr->crypto_mmo.gcm_256_decrypt =
1176 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_decrypt);
1177 : 0 : attr->crypto_mmo.gcm_128_decrypt =
1178 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_decrypt);
1179 : 0 : attr->crypto_mmo.gcm_auth_tag_128 =
1180 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_128);
1181 : 0 : attr->crypto_mmo.gcm_auth_tag_96 =
1182 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_96);
1183 : 0 : attr->crypto_mmo.log_crypto_mmo_max_size =
1184 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, log_crypto_mmo_max_size);
1185 : : }
1186 [ # # ]: 0 : if (hca_cap_2_sup) {
1187 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1188 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
1189 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1190 [ # # ]: 0 : if (!hcattr) {
1191 : 0 : DRV_LOG(DEBUG,
1192 : : "Failed to query DevX HCA capabilities 2.");
1193 : 0 : return rc;
1194 : : }
1195 [ # # ]: 0 : attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr,
1196 : : log_min_stride_wqe_sz);
1197 [ # # ]: 0 : attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr,
1198 : : hairpin_sq_wqe_bb_size);
1199 [ # # ]: 0 : attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr,
1200 : : hairpin_sq_wq_in_host_mem);
1201 [ # # ]: 0 : attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr,
1202 : : hairpin_data_buffer_locked);
1203 [ # # ]: 0 : attr->flow_counter_bulk_log_max_alloc = MLX5_GET(cmd_hca_cap_2,
1204 : : hcattr, flow_counter_bulk_log_max_alloc);
1205 : 0 : attr->flow_counter_bulk_log_granularity =
1206 [ # # ]: 0 : MLX5_GET(cmd_hca_cap_2, hcattr,
1207 : : flow_counter_bulk_log_granularity);
1208 [ # # ]: 0 : rc = MLX5_GET(cmd_hca_cap_2, hcattr,
1209 : : cross_vhca_object_to_object_supported);
1210 : 0 : attr->cross_vhca =
1211 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR) &&
1212 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT) &&
1213 : 0 : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT) &&
1214 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC);
1215 [ # # ]: 0 : rc = MLX5_GET(cmd_hca_cap_2, hcattr,
1216 : : allowed_object_for_other_vhca_access);
1217 : 0 : attr->cross_vhca = attr->cross_vhca &&
1218 : : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR) &&
1219 [ # # # # ]: 0 : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) &&
1220 : : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC);
1221 [ # # ]: 0 : if (attr->ct_offload)
1222 [ # # ]: 0 : attr->log_max_conn_track_offload = MLX5_GET(cmd_hca_cap_2, hcattr,
1223 : : log_max_conn_track_offload);
1224 : : }
1225 [ # # ]: 0 : if (attr->log_min_stride_wqe_sz == 0)
1226 : 0 : attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;
1227 [ # # ]: 0 : if (attr->qos.sup) {
1228 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1229 : : MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
1230 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1231 [ # # ]: 0 : if (!hcattr) {
1232 : 0 : DRV_LOG(DEBUG, "Failed to query devx QOS capabilities");
1233 : 0 : return rc;
1234 : : }
1235 : 0 : attr->qos.flow_meter_old =
1236 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, flow_meter_old);
1237 : 0 : attr->qos.log_max_flow_meter =
1238 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
1239 [ # # ]: 0 : attr->qos.flow_meter_reg_c_ids =
1240 : : MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
1241 : 0 : attr->qos.flow_meter =
1242 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, flow_meter);
1243 : 0 : attr->qos.packet_pacing =
1244 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, packet_pacing);
1245 : 0 : attr->qos.wqe_rate_pp =
1246 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
1247 : 0 : attr->qos.packet_pacing_burst_bound =
1248 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1249 : : packet_pacing_burst_bound);
1250 : 0 : attr->qos.packet_pacing_typical_size =
1251 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1252 : : packet_pacing_typical_size);
1253 : 0 : attr->qos.packet_pacing_max_rate =
1254 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1255 : : packet_pacing_max_rate);
1256 : 0 : attr->qos.packet_pacing_min_rate =
1257 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1258 : : packet_pacing_min_rate);
1259 : 0 : attr->qos.packet_pacing_rate_table_size =
1260 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1261 : : packet_pacing_rate_table_size);
1262 [ # # ]: 0 : if (attr->qos.flow_meter_aso_sup) {
1263 : 0 : attr->qos.log_meter_aso_granularity =
1264 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1265 : : log_meter_aso_granularity);
1266 : 0 : attr->qos.log_meter_aso_max_alloc =
1267 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1268 : : log_meter_aso_max_alloc);
1269 : 0 : attr->qos.log_max_num_meter_aso =
1270 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1271 : : log_max_num_meter_aso);
1272 : : }
1273 : : }
1274 [ # # ]: 0 : if (attr->vdpa.valid)
1275 : 0 : mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
1276 [ # # ]: 0 : if (!attr->eth_net_offloads)
1277 : : return 0;
1278 : : /* Query Flow Sampler Capability From FLow Table Properties Layout. */
1279 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1280 : : MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
1281 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1282 [ # # ]: 0 : if (!hcattr) {
1283 : 0 : attr->log_max_ft_sampler_num = 0;
1284 : 0 : return rc;
1285 : : }
1286 [ # # ]: 0 : attr->log_max_ft_sampler_num = MLX5_GET
1287 : : (flow_table_nic_cap, hcattr,
1288 : : flow_table_properties_nic_receive.log_max_ft_sampler_num);
1289 [ # # ]: 0 : attr->flow.tunnel_header_0_1 = MLX5_GET
1290 : : (flow_table_nic_cap, hcattr,
1291 : : ft_field_support_2_nic_receive.tunnel_header_0_1);
1292 [ # # ]: 0 : attr->flow.tunnel_header_2_3 = MLX5_GET
1293 : : (flow_table_nic_cap, hcattr,
1294 : : ft_field_support_2_nic_receive.tunnel_header_2_3);
1295 [ # # ]: 0 : attr->modify_outer_ip_ecn = MLX5_GET
1296 : : (flow_table_nic_cap, hcattr,
1297 : : ft_header_modify_nic_receive.outer_ip_ecn);
1298 [ # # ]: 0 : attr->modify_outer_ipv6_traffic_class = MLX5_GET
1299 : : (flow_table_nic_cap, hcattr,
1300 : : ft_header_modify_nic_receive.outer_ipv6_traffic_class);
1301 : 0 : attr->set_reg_c = 0xffff;
1302 [ # # ]: 0 : if (attr->nic_flow_table) {
1303 : : #define GET_RX_REG_X_BITS \
1304 : : MLX5_GET(flow_table_nic_cap, hcattr, \
1305 : : ft_header_modify_nic_receive.metadata_reg_c_x)
1306 : : #define GET_TX_REG_X_BITS \
1307 : : MLX5_GET(flow_table_nic_cap, hcattr, \
1308 : : ft_header_modify_nic_transmit.metadata_reg_c_x)
1309 : :
1310 : : uint32_t tx_reg, rx_reg, reg_c_8_15;
1311 : :
1312 [ # # ]: 0 : tx_reg = GET_TX_REG_X_BITS;
1313 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr,
1314 : : ft_field_support_2_nic_transmit.metadata_reg_c_8_15);
1315 : 0 : tx_reg |= ((0xff & reg_c_8_15) << 8);
1316 [ # # ]: 0 : rx_reg = GET_RX_REG_X_BITS;
1317 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr,
1318 : : ft_field_support_2_nic_receive.metadata_reg_c_8_15);
1319 : 0 : rx_reg |= ((0xff & reg_c_8_15) << 8);
1320 : 0 : attr->set_reg_c &= (rx_reg & tx_reg);
1321 : :
1322 [ # # ]: 0 : attr->rx_sw_owner_v2 = MLX5_GET(flow_table_nic_cap, hcattr,
1323 : : flow_table_properties_nic_receive.sw_owner_v2);
1324 [ # # ]: 0 : if (!attr->rx_sw_owner_v2)
1325 [ # # ]: 0 : attr->rx_sw_owner = MLX5_GET(flow_table_nic_cap, hcattr,
1326 : : flow_table_properties_nic_receive.sw_owner);
1327 : :
1328 [ # # ]: 0 : attr->tx_sw_owner_v2 = MLX5_GET(flow_table_nic_cap, hcattr,
1329 : : flow_table_properties_nic_transmit.sw_owner_v2);
1330 [ # # ]: 0 : if (!attr->tx_sw_owner_v2)
1331 [ # # ]: 0 : attr->tx_sw_owner = MLX5_GET(flow_table_nic_cap, hcattr,
1332 : : flow_table_properties_nic_transmit.sw_owner);
1333 : :
1334 : : #undef GET_RX_REG_X_BITS
1335 : : #undef GET_TX_REG_X_BITS
1336 : : }
1337 : 0 : attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
1338 [ # # ]: 0 : attr->inner_ipv4_ihl = MLX5_GET
1339 : : (flow_table_nic_cap, hcattr,
1340 : : ft_field_support_2_nic_receive.inner_ipv4_ihl);
1341 [ # # ]: 0 : attr->outer_ipv4_ihl = MLX5_GET
1342 : : (flow_table_nic_cap, hcattr,
1343 : : ft_field_support_2_nic_receive.outer_ipv4_ihl);
1344 [ # # ]: 0 : attr->lag_rx_port_affinity = MLX5_GET
1345 : : (flow_table_nic_cap, hcattr,
1346 : : ft_field_support_2_nic_receive.lag_rx_port_affinity);
1347 : : /* Query HCA offloads for Ethernet protocol. */
1348 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1349 : : MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
1350 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1351 [ # # ]: 0 : if (!hcattr) {
1352 : 0 : attr->eth_net_offloads = 0;
1353 : 0 : return rc;
1354 : : }
1355 [ # # ]: 0 : attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
1356 : : hcattr, wqe_vlan_insert);
1357 [ # # ]: 0 : attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,
1358 : : hcattr, csum_cap);
1359 [ # # ]: 0 : attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps,
1360 : : hcattr, vlan_cap);
1361 [ # # ]: 0 : attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1362 : : lro_cap);
1363 [ # # ]: 0 : attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps,
1364 : : hcattr, max_lso_cap);
1365 [ # # ]: 0 : attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps,
1366 : : hcattr, scatter_fcs);
1367 [ # # ]: 0 : attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
1368 : : hcattr, tunnel_lro_gre);
1369 [ # # ]: 0 : attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
1370 : : hcattr, tunnel_lro_vxlan);
1371 [ # # ]: 0 : attr->swp = MLX5_GET(per_protocol_networking_offload_caps,
1372 : : hcattr, swp);
1373 : 0 : attr->tunnel_stateless_gre =
1374 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1375 : : hcattr, tunnel_stateless_gre);
1376 : 0 : attr->tunnel_stateless_vxlan =
1377 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1378 : : hcattr, tunnel_stateless_vxlan);
1379 [ # # ]: 0 : attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps,
1380 : : hcattr, swp_csum);
1381 [ # # ]: 0 : attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps,
1382 : : hcattr, swp_lso);
1383 [ # # ]: 0 : attr->lro_max_msg_sz_mode = MLX5_GET
1384 : : (per_protocol_networking_offload_caps,
1385 : : hcattr, lro_max_msg_sz_mode);
1386 [ # # ]: 0 : for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
1387 : 0 : attr->lro_timer_supported_periods[i] =
1388 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1389 : : lro_timer_supported_periods[i]);
1390 : : }
1391 [ # # ]: 0 : attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
1392 : : hcattr, lro_min_mss_size);
1393 : 0 : attr->tunnel_stateless_geneve_rx =
1394 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1395 : : hcattr, tunnel_stateless_geneve_rx);
1396 : 0 : attr->geneve_max_opt_len =
1397 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1398 : : hcattr, max_geneve_opt_len);
1399 [ # # ]: 0 : attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
1400 : : hcattr, wqe_inline_mode);
1401 [ # # ]: 0 : attr->tunnel_stateless_gtp = MLX5_GET
1402 : : (per_protocol_networking_offload_caps,
1403 : : hcattr, tunnel_stateless_gtp);
1404 [ # # ]: 0 : attr->tunnel_stateless_vxlan_gpe_nsh = MLX5_GET
1405 : : (per_protocol_networking_offload_caps,
1406 : : hcattr, tunnel_stateless_vxlan_gpe_nsh);
1407 [ # # ]: 0 : attr->rss_ind_tbl_cap = MLX5_GET
1408 : : (per_protocol_networking_offload_caps,
1409 : : hcattr, rss_ind_tbl_cap);
1410 [ # # ]: 0 : attr->multi_pkt_send_wqe = MLX5_GET
1411 : : (per_protocol_networking_offload_caps,
1412 : : hcattr, multi_pkt_send_wqe);
1413 [ # # ]: 0 : attr->enhanced_multi_pkt_send_wqe = MLX5_GET
1414 : : (per_protocol_networking_offload_caps,
1415 : : hcattr, enhanced_multi_pkt_send_wqe);
1416 [ # # ]: 0 : if (attr->wqe_based_flow_table_sup) {
1417 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1418 : : MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE |
1419 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1420 [ # # ]: 0 : if (!hcattr) {
1421 : 0 : DRV_LOG(DEBUG, "Failed to query WQE Based Flow table capabilities");
1422 : 0 : return rc;
1423 : : }
1424 [ # # ]: 0 : attr->max_header_modify_pattern_length = MLX5_GET(wqe_based_flow_table_cap,
1425 : : hcattr,
1426 : : max_header_modify_pattern_length);
1427 [ # # ]: 0 : attr->fdb_unified_en = MLX5_GET(wqe_based_flow_table_cap,
1428 : : hcattr,
1429 : : fdb_unified_en);
1430 [ # # ]: 0 : attr->fdb_rx_set_flow_tag_stc = MLX5_GET(wqe_based_flow_table_cap,
1431 : : hcattr,
1432 : : fdb_rx_set_flow_tag_stc);
1433 [ # # ]: 0 : stc_action_type_127_64 = MLX5_GET64(wqe_based_flow_table_cap,
1434 : : hcattr,
1435 : : stc_action_type_127_64);
1436 [ # # ]: 0 : if (stc_action_type_127_64 &
1437 : : (1 << (MLX5_IFC_STC_ACTION_TYPE_JUMP_FLOW_TABLE_FDB_RX_BIT_INDEX -
1438 : : MLX5_IFC_STC_ACTION_TYPE_BIT_64_INDEX)))
1439 : 0 : attr->jump_fdb_rx_en = 1;
1440 : : }
1441 : : /* Query HCA attribute for ROCE. */
1442 [ # # ]: 0 : if (attr->roce) {
1443 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1444 : : MLX5_GET_HCA_CAP_OP_MOD_ROCE |
1445 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1446 [ # # ]: 0 : if (!hcattr) {
1447 : 0 : DRV_LOG(DEBUG,
1448 : : "Failed to query devx HCA ROCE capabilities");
1449 : 0 : return rc;
1450 : : }
1451 [ # # ]: 0 : attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
1452 : : }
1453 [ # # ]: 0 : if (attr->eth_virt) {
1454 : 0 : rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
1455 [ # # ]: 0 : if (rc) {
1456 : 0 : attr->eth_virt = 0;
1457 : 0 : goto error;
1458 : : }
1459 : : }
1460 [ # # ]: 0 : if (attr->eswitch_manager) {
1461 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1462 : : MLX5_SET_HCA_CAP_OP_MOD_ESW |
1463 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1464 [ # # ]: 0 : if (!hcattr)
1465 : 0 : return rc;
1466 : 0 : attr->esw_mgr_vport_id_valid =
1467 [ # # ]: 0 : MLX5_GET(esw_cap, hcattr,
1468 : : esw_manager_vport_number_valid);
1469 : 0 : attr->esw_mgr_vport_id =
1470 [ # # ]: 0 : MLX5_GET(esw_cap, hcattr, esw_manager_vport_number);
1471 : 0 : mlx5_devx_cmd_query_esw_vport_context(ctx, attr);
1472 : : }
1473 [ # # ]: 0 : if (attr->eswitch_manager) {
1474 : : uint32_t esw_reg, reg_c_8_15;
1475 : :
1476 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1477 : : MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE |
1478 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1479 [ # # ]: 0 : if (!hcattr)
1480 : 0 : return rc;
1481 [ # # ]: 0 : esw_reg = MLX5_GET(flow_table_esw_cap, hcattr,
1482 : : ft_header_modify_esw_fdb.metadata_reg_c_x);
1483 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_esw_cap, hcattr,
1484 : : ft_field_support_2_esw_fdb.metadata_reg_c_8_15);
1485 : 0 : attr->set_reg_c &= ((0xff & reg_c_8_15) << 8) | esw_reg;
1486 : :
1487 [ # # ]: 0 : attr->esw_sw_owner_v2 = MLX5_GET(flow_table_esw_cap, hcattr,
1488 : : flow_table_properties_nic_esw_fdb.sw_owner_v2);
1489 [ # # ]: 0 : if (!attr->esw_sw_owner_v2)
1490 [ # # ]: 0 : attr->esw_sw_owner = MLX5_GET(flow_table_esw_cap, hcattr,
1491 : : flow_table_properties_nic_esw_fdb.sw_owner);
1492 : : }
1493 : : return 0;
1494 : : error:
1495 : 0 : rc = (rc > 0) ? -rc : rc;
1496 : 0 : return rc;
1497 : : }
1498 : :
1499 : : /**
1500 : : * Query TIS transport domain from QP verbs object using DevX API.
1501 : : *
1502 : : * @param[in] qp
1503 : : * Pointer to verbs QP returned by ibv_create_qp .
1504 : : * @param[in] tis_num
1505 : : * TIS number of TIS to query.
1506 : : * @param[out] tis_td
1507 : : * Pointer to TIS transport domain variable, to be set by the routine.
1508 : : *
1509 : : * @return
1510 : : * 0 on success, a negative value otherwise.
1511 : : */
1512 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_qp_query_tis_td)
1513 : : int
1514 : 0 : mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
1515 : : uint32_t *tis_td)
1516 : : {
1517 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1518 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
1519 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
1520 : : int rc;
1521 : : void *tis_ctx;
1522 : :
1523 : 0 : MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
1524 : 0 : MLX5_SET(query_tis_in, in, tisn, tis_num);
1525 : 0 : rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
1526 [ # # ]: 0 : if (rc) {
1527 : 0 : DRV_LOG(ERR, "Failed to query QP using DevX");
1528 : 0 : return -rc;
1529 : : };
1530 : : tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
1531 [ # # ]: 0 : *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
1532 : 0 : return 0;
1533 : : #else
1534 : : (void)qp;
1535 : : (void)tis_num;
1536 : : (void)tis_td;
1537 : : return -ENOTSUP;
1538 : : #endif
1539 : : }
1540 : :
1541 : : /**
1542 : : * Fill WQ data for DevX API command.
1543 : : * Utility function for use when creating DevX objects containing a WQ.
1544 : : *
1545 : : * @param[in] wq_ctx
1546 : : * Pointer to WQ context to fill with data.
1547 : : * @param [in] wq_attr
1548 : : * Pointer to WQ attributes structure to fill in WQ context.
1549 : : */
1550 : : static void
1551 : 0 : devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
1552 : : {
1553 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
1554 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
1555 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
1556 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
1557 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
1558 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
1559 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
1560 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
1561 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
1562 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
1563 [ # # ]: 0 : MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1564 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1565 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1566 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1567 [ # # ]: 0 : if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1568 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1569 : : wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1570 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1571 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1572 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1573 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1574 : : wq_attr->log_hairpin_num_packets);
1575 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1576 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1577 : : wq_attr->single_wqe_log_num_of_strides);
1578 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1579 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1580 : : wq_attr->single_stride_log_num_of_bytes);
1581 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1582 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1583 [ # # ]: 0 : MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1584 : 0 : }
1585 : :
1586 : : /**
1587 : : * Create RQ using DevX API.
1588 : : *
1589 : : * @param[in] ctx
1590 : : * Context returned from mlx5 open_device() glue function.
1591 : : * @param [in] rq_attr
1592 : : * Pointer to create RQ attributes structure.
1593 : : * @param [in] socket
1594 : : * CPU socket ID for allocations.
1595 : : *
1596 : : * @return
1597 : : * The DevX object created, NULL otherwise and rte_errno is set.
1598 : : */
1599 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_rq)
1600 : : struct mlx5_devx_obj *
1601 : 0 : mlx5_devx_cmd_create_rq(void *ctx,
1602 : : struct mlx5_devx_create_rq_attr *rq_attr,
1603 : : int socket)
1604 : : {
1605 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1606 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1607 : : void *rq_ctx, *wq_ctx;
1608 : : struct mlx5_devx_wq_attr *wq_attr;
1609 : : struct mlx5_devx_obj *rq = NULL;
1610 : :
1611 [ # # # # ]: 0 : rq = mlx5_malloc_numa_tolerant(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1612 [ # # ]: 0 : if (!rq) {
1613 : 0 : DRV_LOG(ERR, "Failed to allocate RQ data");
1614 : 0 : rte_errno = ENOMEM;
1615 : 0 : return NULL;
1616 : : }
1617 [ # # ]: 0 : MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1618 : : rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1619 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1620 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1621 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1622 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1623 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1624 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1625 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1626 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1627 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type);
1628 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1629 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1630 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1631 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1632 [ # # ]: 0 : MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1633 : : wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1634 : 0 : wq_attr = &rq_attr->wq_attr;
1635 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1636 : 0 : rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1637 : : out, sizeof(out));
1638 [ # # ]: 0 : if (!rq->obj) {
1639 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0);
1640 : 0 : mlx5_free(rq);
1641 : 0 : return NULL;
1642 : : }
1643 [ # # ]: 0 : rq->id = MLX5_GET(create_rq_out, out, rqn);
1644 : 0 : return rq;
1645 : : }
1646 : :
1647 : : /**
1648 : : * Modify RQ using DevX API.
1649 : : *
1650 : : * @param[in] rq
1651 : : * Pointer to RQ object structure.
1652 : : * @param [in] rq_attr
1653 : : * Pointer to modify RQ attributes structure.
1654 : : *
1655 : : * @return
1656 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
1657 : : */
1658 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_rq)
1659 : : int
1660 : 0 : mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1661 : : struct mlx5_devx_modify_rq_attr *rq_attr)
1662 : : {
1663 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1664 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1665 : : void *rq_ctx, *wq_ctx;
1666 : : int ret;
1667 : :
1668 : 0 : MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1669 : 0 : MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1670 [ # # ]: 0 : MLX5_SET(modify_rq_in, in, rqn, rq->id);
1671 [ # # ]: 0 : MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1672 : : rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1673 : 0 : MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1674 [ # # ]: 0 : if (rq_attr->modify_bitmask &
1675 : : MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1676 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1677 [ # # ]: 0 : if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1678 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1679 [ # # ]: 0 : if (rq_attr->modify_bitmask &
1680 : : MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1681 : 0 : MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1682 : 0 : MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1683 : 0 : MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1684 [ # # ]: 0 : if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1685 : : wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1686 : 0 : MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1687 : : }
1688 : 0 : ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1689 : : out, sizeof(out));
1690 [ # # # # : 0 : if (ret || MLX5_FW_STATUS(out)) {
# # # # ]
1691 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "RQ modify", "rq_id", rq->id);
1692 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(ret);
1693 : : }
1694 : : return 0;
1695 : : }
1696 : :
1697 : : /*
1698 : : * Query RQ using DevX API.
1699 : : *
1700 : : * @param[in] rq_obj
1701 : : * RQ Devx Object
1702 : : * @param[out] out
1703 : : * RQ Query Output
1704 : : * @param[in] outlen
1705 : : * RQ Query Output Length
1706 : : *
1707 : : * @return
1708 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
1709 : : */
1710 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_rq)
1711 : : int
1712 : 0 : mlx5_devx_cmd_query_rq(struct mlx5_devx_obj *rq_obj, void *out, size_t outlen)
1713 : : {
1714 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
1715 : : int rc;
1716 : :
1717 : 0 : MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
1718 : 0 : MLX5_SET(query_rq_in, in, rqn, rq_obj->id);
1719 : 0 : rc = mlx5_glue->devx_obj_query(rq_obj->obj, in, sizeof(in), out, outlen);
1720 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
1721 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "RQ query", "rq_id", rq_obj->id);
1722 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
1723 : : }
1724 : : return 0;
1725 : : }
1726 : :
1727 : : /**
1728 : : * Create RMP using DevX API.
1729 : : *
1730 : : * @param[in] ctx
1731 : : * Context returned from mlx5 open_device() glue function.
1732 : : * @param [in] rmp_attr
1733 : : * Pointer to create RMP attributes structure.
1734 : : * @param [in] socket
1735 : : * CPU socket ID for allocations.
1736 : : *
1737 : : * @return
1738 : : * The DevX object created, NULL otherwise and rte_errno is set.
1739 : : */
1740 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_rmp)
1741 : : struct mlx5_devx_obj *
1742 : 0 : mlx5_devx_cmd_create_rmp(void *ctx,
1743 : : struct mlx5_devx_create_rmp_attr *rmp_attr,
1744 : : int socket)
1745 : : {
1746 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0};
1747 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0};
1748 : : void *rmp_ctx, *wq_ctx;
1749 : : struct mlx5_devx_wq_attr *wq_attr;
1750 : : struct mlx5_devx_obj *rmp = NULL;
1751 : :
1752 [ # # # # ]: 0 : rmp = mlx5_malloc_numa_tolerant(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket);
1753 [ # # ]: 0 : if (!rmp) {
1754 : 0 : DRV_LOG(ERR, "Failed to allocate RMP data");
1755 : 0 : rte_errno = ENOMEM;
1756 : 0 : return NULL;
1757 : : }
1758 [ # # ]: 0 : MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP);
1759 : : rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx);
1760 [ # # ]: 0 : MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state);
1761 [ # # ]: 0 : MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe,
1762 : : rmp_attr->basic_cyclic_rcv_wqe);
1763 : : wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq);
1764 : 0 : wq_attr = &rmp_attr->wq_attr;
1765 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1766 : 0 : rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1767 : : sizeof(out));
1768 [ # # ]: 0 : if (!rmp->obj) {
1769 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0);
1770 : 0 : mlx5_free(rmp);
1771 : 0 : return NULL;
1772 : : }
1773 [ # # ]: 0 : rmp->id = MLX5_GET(create_rmp_out, out, rmpn);
1774 : 0 : return rmp;
1775 : : }
1776 : :
1777 : : /*
1778 : : * Create TIR using DevX API.
1779 : : *
1780 : : * @param[in] ctx
1781 : : * Context returned from mlx5 open_device() glue function.
1782 : : * @param [in] tir_attr
1783 : : * Pointer to TIR attributes structure.
1784 : : *
1785 : : * @return
1786 : : * The DevX object created, NULL otherwise and rte_errno is set.
1787 : : */
1788 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_tir)
1789 : : struct mlx5_devx_obj *
1790 : 0 : mlx5_devx_cmd_create_tir(void *ctx,
1791 : : struct mlx5_devx_tir_attr *tir_attr)
1792 : : {
1793 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1794 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1795 : : void *tir_ctx, *outer, *inner, *rss_key;
1796 : : struct mlx5_devx_obj *tir = NULL;
1797 : :
1798 : 0 : tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1799 [ # # ]: 0 : if (!tir) {
1800 : 0 : DRV_LOG(ERR, "Failed to allocate TIR data");
1801 : 0 : rte_errno = ENOMEM;
1802 : 0 : return NULL;
1803 : : }
1804 [ # # ]: 0 : MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1805 : : tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1806 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1807 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1808 : : tir_attr->lro_timeout_period_usecs);
1809 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1810 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1811 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1812 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1813 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1814 : : tir_attr->tunneled_offload_en);
1815 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1816 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1817 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1818 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1819 : : rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1820 [ # # ]: 0 : memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1821 : : outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1822 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1823 : : tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1824 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1825 : : tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1826 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, selected_fields,
1827 : : tir_attr->rx_hash_field_selector_outer.selected_fields);
1828 : : inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1829 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1830 : : tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1831 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1832 : : tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1833 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, selected_fields,
1834 : : tir_attr->rx_hash_field_selector_inner.selected_fields);
1835 : 0 : tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1836 : : out, sizeof(out));
1837 [ # # ]: 0 : if (!tir->obj) {
1838 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0);
1839 : 0 : mlx5_free(tir);
1840 : 0 : return NULL;
1841 : : }
1842 [ # # ]: 0 : tir->id = MLX5_GET(create_tir_out, out, tirn);
1843 : 0 : return tir;
1844 : : }
1845 : :
1846 : : /**
1847 : : * Modify TIR using DevX API.
1848 : : *
1849 : : * @param[in] tir
1850 : : * Pointer to TIR DevX object structure.
1851 : : * @param [in] modify_tir_attr
1852 : : * Pointer to TIR modification attributes structure.
1853 : : *
1854 : : * @return
1855 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
1856 : : */
1857 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_tir)
1858 : : int
1859 : 0 : mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1860 : : struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1861 : : {
1862 : : struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1863 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1864 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1865 : : void *tir_ctx;
1866 : : int ret;
1867 : :
1868 : 0 : MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1869 : 0 : MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1870 [ # # ]: 0 : MLX5_SET64(modify_tir_in, in, modify_bitmask,
1871 : : modify_tir_attr->modify_bitmask);
1872 : : tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1873 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1874 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1875 : 0 : MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1876 : : tir_attr->lro_timeout_period_usecs);
1877 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1878 : : tir_attr->lro_enable_mask);
1879 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1880 : : tir_attr->lro_max_msg_sz);
1881 : : }
1882 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1883 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1884 : 0 : MLX5_SET(tirc, tir_ctx, indirect_table,
1885 : : tir_attr->indirect_table);
1886 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1887 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1888 : : int i;
1889 : : void *outer, *inner;
1890 : :
1891 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1892 : : tir_attr->rx_hash_symmetric);
1893 : 0 : MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1894 [ # # ]: 0 : for (i = 0; i < 10; i++) {
1895 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1896 : : tir_attr->rx_hash_toeplitz_key[i]);
1897 : : }
1898 : : outer = MLX5_ADDR_OF(tirc, tir_ctx,
1899 : : rx_hash_field_selector_outer);
1900 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1901 : : tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1902 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1903 : : tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1904 [ # # ]: 0 : MLX5_SET
1905 : : (rx_hash_field_select, outer, selected_fields,
1906 : : tir_attr->rx_hash_field_selector_outer.selected_fields);
1907 : : inner = MLX5_ADDR_OF(tirc, tir_ctx,
1908 : : rx_hash_field_selector_inner);
1909 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1910 : : tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1911 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1912 : : tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1913 [ # # ]: 0 : MLX5_SET
1914 : : (rx_hash_field_select, inner, selected_fields,
1915 : : tir_attr->rx_hash_field_selector_inner.selected_fields);
1916 : : }
1917 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1918 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1919 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1920 : : }
1921 : 0 : ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1922 : : out, sizeof(out));
1923 [ # # ]: 0 : if (ret) {
1924 : 0 : DRV_LOG(ERR, "Failed to modify TIR using DevX");
1925 : 0 : rte_errno = errno;
1926 : 0 : return -errno;
1927 : : }
1928 : : return ret;
1929 : : }
1930 : :
1931 : : /**
1932 : : * Create RQT using DevX API.
1933 : : *
1934 : : * @param[in] ctx
1935 : : * Context returned from mlx5 open_device() glue function.
1936 : : * @param [in] rqt_attr
1937 : : * Pointer to RQT attributes structure.
1938 : : *
1939 : : * @return
1940 : : * The DevX object created, NULL otherwise and rte_errno is set.
1941 : : */
1942 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_rqt)
1943 : : struct mlx5_devx_obj *
1944 : 0 : mlx5_devx_cmd_create_rqt(void *ctx,
1945 : : struct mlx5_devx_rqt_attr *rqt_attr)
1946 : : {
1947 : : uint32_t *in = NULL;
1948 : 0 : uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1949 : 0 : rqt_attr->rqt_actual_size * sizeof(uint32_t);
1950 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1951 : : void *rqt_ctx;
1952 : : struct mlx5_devx_obj *rqt = NULL;
1953 : : unsigned int i;
1954 : :
1955 : 0 : in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1956 [ # # ]: 0 : if (!in) {
1957 : 0 : DRV_LOG(ERR, "Failed to allocate RQT IN data");
1958 : 0 : rte_errno = ENOMEM;
1959 : 0 : return NULL;
1960 : : }
1961 : 0 : rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1962 [ # # ]: 0 : if (!rqt) {
1963 : 0 : DRV_LOG(ERR, "Failed to allocate RQT data");
1964 : 0 : rte_errno = ENOMEM;
1965 : 0 : mlx5_free(in);
1966 : 0 : return NULL;
1967 : : }
1968 [ # # ]: 0 : MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1969 : 0 : rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1970 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1971 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1972 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1973 [ # # ]: 0 : for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1974 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1975 : 0 : rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1976 : 0 : mlx5_free(in);
1977 [ # # ]: 0 : if (!rqt->obj) {
1978 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0);
1979 : 0 : mlx5_free(rqt);
1980 : 0 : return NULL;
1981 : : }
1982 [ # # ]: 0 : rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1983 : 0 : return rqt;
1984 : : }
1985 : :
1986 : : /**
1987 : : * Modify RQT using DevX API.
1988 : : *
1989 : : * @param[in] rqt
1990 : : * Pointer to RQT DevX object structure.
1991 : : * @param [in] rqt_attr
1992 : : * Pointer to RQT attributes structure.
1993 : : *
1994 : : * @return
1995 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
1996 : : */
1997 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_rqt)
1998 : : int
1999 : 0 : mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
2000 : : struct mlx5_devx_rqt_attr *rqt_attr)
2001 : : {
2002 : 0 : uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
2003 : 0 : rqt_attr->rqt_actual_size * sizeof(uint32_t);
2004 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
2005 : 0 : uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
2006 : : void *rqt_ctx;
2007 : : unsigned int i;
2008 : : int ret;
2009 : :
2010 [ # # ]: 0 : if (!in) {
2011 : 0 : DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
2012 : 0 : rte_errno = ENOMEM;
2013 : 0 : return -ENOMEM;
2014 : : }
2015 [ # # ]: 0 : MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
2016 [ # # ]: 0 : MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
2017 : 0 : MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
2018 : 0 : rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
2019 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
2020 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
2021 [ # # ]: 0 : for (i = 0; i < rqt_attr->rqt_actual_size; i++)
2022 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
2023 : 0 : ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
2024 : 0 : mlx5_free(in);
2025 [ # # ]: 0 : if (ret) {
2026 : 0 : DRV_LOG(ERR, "Failed to modify RQT using DevX.");
2027 : 0 : rte_errno = errno;
2028 : 0 : return -rte_errno;
2029 : : }
2030 : : return ret;
2031 : : }
2032 : :
2033 : : /**
2034 : : * Create SQ using DevX API.
2035 : : *
2036 : : * @param[in] ctx
2037 : : * Context returned from mlx5 open_device() glue function.
2038 : : * @param [in] sq_attr
2039 : : * Pointer to SQ attributes structure.
2040 : : * @param [in] socket
2041 : : * CPU socket ID for allocations.
2042 : : *
2043 : : * @return
2044 : : * The DevX object created, NULL otherwise and rte_errno is set.
2045 : : **/
2046 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_sq)
2047 : : struct mlx5_devx_obj *
2048 : 0 : mlx5_devx_cmd_create_sq(void *ctx,
2049 : : struct mlx5_devx_create_sq_attr *sq_attr)
2050 : : {
2051 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
2052 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
2053 : : void *sq_ctx;
2054 : : void *wq_ctx;
2055 : : struct mlx5_devx_wq_attr *wq_attr;
2056 : : struct mlx5_devx_obj *sq = NULL;
2057 : :
2058 : 0 : sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
2059 [ # # ]: 0 : if (!sq) {
2060 : 0 : DRV_LOG(ERR, "Failed to allocate SQ data");
2061 : 0 : rte_errno = ENOMEM;
2062 : 0 : return NULL;
2063 : : }
2064 [ # # ]: 0 : MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
2065 : : sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
2066 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
2067 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
2068 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
2069 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
2070 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
2071 : : sq_attr->allow_multi_pkt_send_wqe);
2072 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
2073 : : sq_attr->min_wqe_inline_mode);
2074 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
2075 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
2076 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
2077 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
2078 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
2079 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
2080 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type);
2081 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
2082 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
2083 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
2084 : : sq_attr->packet_pacing_rate_limit_index);
2085 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
2086 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
2087 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
2088 : : wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
2089 : 0 : wq_attr = &sq_attr->wq_attr;
2090 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
2091 : 0 : sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2092 : : out, sizeof(out));
2093 [ # # ]: 0 : if (!sq->obj) {
2094 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0);
2095 : 0 : mlx5_free(sq);
2096 : 0 : return NULL;
2097 : : }
2098 [ # # ]: 0 : sq->id = MLX5_GET(create_sq_out, out, sqn);
2099 : 0 : return sq;
2100 : : }
2101 : :
2102 : : /**
2103 : : * Modify SQ using DevX API.
2104 : : *
2105 : : * @param[in] sq
2106 : : * Pointer to SQ object structure.
2107 : : * @param [in] sq_attr
2108 : : * Pointer to SQ attributes structure.
2109 : : *
2110 : : * @return
2111 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2112 : : */
2113 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_sq)
2114 : : int
2115 : 0 : mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
2116 : : struct mlx5_devx_modify_sq_attr *sq_attr)
2117 : : {
2118 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
2119 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
2120 : : void *sq_ctx;
2121 : : int ret;
2122 : :
2123 : 0 : MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
2124 : 0 : MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
2125 [ # # ]: 0 : MLX5_SET(modify_sq_in, in, sqn, sq->id);
2126 : : sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2127 : 0 : MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
2128 : 0 : MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
2129 : 0 : MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
2130 [ # # ]: 0 : if (sq_attr->rl_update) {
2131 : 0 : uint64_t msk = MLX5_GET64(modify_sq_in, in, modify_bitmask);
2132 : :
2133 : 0 : msk |= MLX5_MODIFY_SQ_IN_MODIFY_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX;
2134 [ # # ]: 0 : MLX5_SET64(modify_sq_in, in, modify_bitmask, msk);
2135 : 0 : MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
2136 : : sq_attr->packet_pacing_rate_limit_index);
2137 : : }
2138 : 0 : ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
2139 : : out, sizeof(out));
2140 [ # # # # : 0 : if (ret || MLX5_FW_STATUS(out)) {
# # # # ]
2141 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "SQ modify", "sq_id", sq->id);
2142 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(ret);
2143 : : }
2144 : : return 0;
2145 : : }
2146 : :
2147 : : /*
2148 : : * Query SQ using DevX API.
2149 : : *
2150 : : * @param[in] sq_obj
2151 : : * SQ Devx Object
2152 : : * @param[out] out
2153 : : * SQ Query Output
2154 : : * @param[in] outlen
2155 : : * SQ Query Output Length
2156 : : *
2157 : : * @return
2158 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
2159 : : */
2160 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_sq)
2161 : : int
2162 : 0 : mlx5_devx_cmd_query_sq(struct mlx5_devx_obj *sq_obj, void *out, size_t outlen)
2163 : : {
2164 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_sq_in)] = {0};
2165 : : int rc;
2166 : :
2167 : 0 : MLX5_SET(query_sq_in, in, opcode, MLX5_CMD_OP_QUERY_SQ);
2168 : 0 : MLX5_SET(query_sq_in, in, sqn, sq_obj->id);
2169 : 0 : rc = mlx5_glue->devx_obj_query(sq_obj->obj, in, sizeof(in), out, outlen);
2170 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
2171 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "SQ query", "sq_id", sq_obj->id);
2172 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
2173 : : }
2174 : : return 0;
2175 : : }
2176 : :
2177 : : /**
2178 : : * Create TIS using DevX API.
2179 : : *
2180 : : * @param[in] ctx
2181 : : * Context returned from mlx5 open_device() glue function.
2182 : : * @param [in] tis_attr
2183 : : * Pointer to TIS attributes structure.
2184 : : *
2185 : : * @return
2186 : : * The DevX object created, NULL otherwise and rte_errno is set.
2187 : : */
2188 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_tis)
2189 : : struct mlx5_devx_obj *
2190 : 0 : mlx5_devx_cmd_create_tis(void *ctx,
2191 : : struct mlx5_devx_tis_attr *tis_attr)
2192 : : {
2193 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2194 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
2195 : : struct mlx5_devx_obj *tis = NULL;
2196 : : void *tis_ctx;
2197 : :
2198 : 0 : tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
2199 [ # # ]: 0 : if (!tis) {
2200 : 0 : DRV_LOG(ERR, "Failed to allocate TIS object");
2201 : 0 : rte_errno = ENOMEM;
2202 : 0 : return NULL;
2203 : : }
2204 [ # # ]: 0 : MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
2205 : : tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
2206 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
2207 : : tis_attr->strict_lag_tx_port_affinity);
2208 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
2209 : : tis_attr->lag_tx_port_affinity);
2210 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
2211 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, transport_domain,
2212 : : tis_attr->transport_domain);
2213 : 0 : tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2214 : : out, sizeof(out));
2215 [ # # ]: 0 : if (!tis->obj) {
2216 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0);
2217 : 0 : mlx5_free(tis);
2218 : 0 : return NULL;
2219 : : }
2220 [ # # ]: 0 : tis->id = MLX5_GET(create_tis_out, out, tisn);
2221 : 0 : return tis;
2222 : : }
2223 : :
2224 : : /**
2225 : : * Create transport domain using DevX API.
2226 : : *
2227 : : * @param[in] ctx
2228 : : * Context returned from mlx5 open_device() glue function.
2229 : : * @return
2230 : : * The DevX object created, NULL otherwise and rte_errno is set.
2231 : : */
2232 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_td)
2233 : : struct mlx5_devx_obj *
2234 : 0 : mlx5_devx_cmd_create_td(void *ctx)
2235 : : {
2236 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
2237 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
2238 : : struct mlx5_devx_obj *td = NULL;
2239 : :
2240 : 0 : td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
2241 [ # # ]: 0 : if (!td) {
2242 : 0 : DRV_LOG(ERR, "Failed to allocate TD object");
2243 : 0 : rte_errno = ENOMEM;
2244 : 0 : return NULL;
2245 : : }
2246 [ # # ]: 0 : MLX5_SET(alloc_transport_domain_in, in, opcode,
2247 : : MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
2248 : 0 : td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2249 : : out, sizeof(out));
2250 [ # # ]: 0 : if (!td->obj) {
2251 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0);
2252 : 0 : mlx5_free(td);
2253 : 0 : return NULL;
2254 : : }
2255 [ # # ]: 0 : td->id = MLX5_GET(alloc_transport_domain_out, out,
2256 : : transport_domain);
2257 : 0 : return td;
2258 : : }
2259 : :
2260 : : /**
2261 : : * Dump all flows to file.
2262 : : *
2263 : : * @param[in] fdb_domain
2264 : : * FDB domain.
2265 : : * @param[in] rx_domain
2266 : : * RX domain.
2267 : : * @param[in] tx_domain
2268 : : * TX domain.
2269 : : * @param[out] file
2270 : : * Pointer to file stream.
2271 : : *
2272 : : * @return
2273 : : * 0 on success, a negative value otherwise.
2274 : : */
2275 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_dump)
2276 : : int
2277 : 0 : mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
2278 : : void *rx_domain __rte_unused,
2279 : : void *tx_domain __rte_unused, FILE *file __rte_unused)
2280 : : {
2281 : : int ret = 0;
2282 : :
2283 : : #ifdef HAVE_MLX5_DR_FLOW_DUMP
2284 [ # # ]: 0 : if (fdb_domain) {
2285 : 0 : ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
2286 [ # # ]: 0 : if (ret)
2287 : : return ret;
2288 : : }
2289 : : MLX5_ASSERT(rx_domain);
2290 : 0 : ret = mlx5_glue->dr_dump_domain(file, rx_domain);
2291 [ # # ]: 0 : if (ret)
2292 : : return ret;
2293 : : MLX5_ASSERT(tx_domain);
2294 : 0 : ret = mlx5_glue->dr_dump_domain(file, tx_domain);
2295 : : #else
2296 : : ret = ENOTSUP;
2297 : : #endif
2298 : 0 : return -ret;
2299 : : }
2300 : :
2301 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_single_dump)
2302 : : int
2303 : 0 : mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
2304 : : FILE *file __rte_unused)
2305 : : {
2306 : : int ret = 0;
2307 : : #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
2308 [ # # ]: 0 : if (rule_info)
2309 : 0 : ret = mlx5_glue->dr_dump_rule(file, rule_info);
2310 : : #else
2311 : : ret = ENOTSUP;
2312 : : #endif
2313 : 0 : return -ret;
2314 : : }
2315 : :
2316 : : /*
2317 : : * Create CQ using DevX API.
2318 : : *
2319 : : * @param[in] ctx
2320 : : * Context returned from mlx5 open_device() glue function.
2321 : : * @param [in] attr
2322 : : * Pointer to CQ attributes structure.
2323 : : *
2324 : : * @return
2325 : : * The DevX object created, NULL otherwise and rte_errno is set.
2326 : : */
2327 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_cq)
2328 : : struct mlx5_devx_obj *
2329 : 0 : mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
2330 : : {
2331 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
2332 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
2333 : 0 : struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
2334 : : sizeof(*cq_obj),
2335 : : 0, SOCKET_ID_ANY);
2336 : : void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2337 : :
2338 [ # # ]: 0 : if (!cq_obj) {
2339 : 0 : DRV_LOG(ERR, "Failed to allocate CQ object memory.");
2340 : 0 : rte_errno = ENOMEM;
2341 : 0 : return NULL;
2342 : : }
2343 [ # # ]: 0 : MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
2344 [ # # ]: 0 : if (attr->db_umem_valid) {
2345 [ # # ]: 0 : MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
2346 [ # # ]: 0 : MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
2347 [ # # ]: 0 : MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
2348 : : } else {
2349 [ # # ]: 0 : MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
2350 : : }
2351 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
2352 : : MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
2353 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
2354 [ # # ]: 0 : MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
2355 [ # # ]: 0 : MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
2356 [ # # ]: 0 : if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2357 [ # # ]: 0 : MLX5_SET(cqc, cqctx, log_page_size,
2358 : : attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2359 [ # # ]: 0 : MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
2360 [ # # ]: 0 : MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
2361 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
2362 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_comp_layout, !!attr->cqe_comp_layout);
2363 [ # # ]: 0 : MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
2364 [ # # ]: 0 : MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
2365 : : attr->mini_cqe_res_format_ext);
2366 [ # # ]: 0 : if (attr->q_umem_valid) {
2367 [ # # ]: 0 : MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
2368 [ # # ]: 0 : MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
2369 [ # # ]: 0 : MLX5_SET64(create_cq_in, in, cq_umem_offset,
2370 : : attr->q_umem_offset);
2371 : : }
2372 : 0 : cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2373 : : sizeof(out));
2374 [ # # ]: 0 : if (!cq_obj->obj) {
2375 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0);
2376 : 0 : mlx5_free(cq_obj);
2377 : 0 : return NULL;
2378 : : }
2379 [ # # ]: 0 : cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
2380 : 0 : return cq_obj;
2381 : : }
2382 : :
2383 : : /*
2384 : : * Query CQ using DevX API.
2385 : : *
2386 : : * @param[in] cq_obj
2387 : : * CQ Devx Object
2388 : : * @param[out] out
2389 : : * CQ Query Output
2390 : : * @param[in] outlen
2391 : : * CQ Query Output Length
2392 : : *
2393 : : * @return
2394 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
2395 : : */
2396 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_cq)
2397 : : int
2398 : 0 : mlx5_devx_cmd_query_cq(struct mlx5_devx_obj *cq_obj, void *out, size_t outlen)
2399 : : {
2400 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_cq_in)] = {0};
2401 : : int rc;
2402 : :
2403 : 0 : MLX5_SET(query_cq_in, in, opcode, MLX5_CMD_OP_QUERY_CQ);
2404 : 0 : MLX5_SET(query_cq_in, in, cqn, cq_obj->id);
2405 : 0 : rc = mlx5_glue->devx_obj_query(cq_obj->obj, in, sizeof(in), out, outlen);
2406 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
2407 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "CQ query", "cq_id", cq_obj->id);
2408 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
2409 : : }
2410 : : return 0;
2411 : : }
2412 : :
2413 : : /**
2414 : : * Create VIRTQ using DevX API.
2415 : : *
2416 : : * @param[in] ctx
2417 : : * Context returned from mlx5 open_device() glue function.
2418 : : * @param [in] attr
2419 : : * Pointer to VIRTQ attributes structure.
2420 : : *
2421 : : * @return
2422 : : * The DevX object created, NULL otherwise and rte_errno is set.
2423 : : */
2424 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_virtq)
2425 : : struct mlx5_devx_obj *
2426 : 0 : mlx5_devx_cmd_create_virtq(void *ctx,
2427 : : struct mlx5_devx_virtq_attr *attr)
2428 : : {
2429 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
2430 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2431 : 0 : struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
2432 : : sizeof(*virtq_obj),
2433 : : 0, SOCKET_ID_ANY);
2434 : : void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
2435 : : void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
2436 : : void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
2437 : :
2438 [ # # ]: 0 : if (!virtq_obj) {
2439 : 0 : DRV_LOG(ERR, "Failed to allocate virtq data.");
2440 : 0 : rte_errno = ENOMEM;
2441 : 0 : return NULL;
2442 : : }
2443 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2444 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2445 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2446 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2447 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, hw_available_index,
2448 : : attr->hw_available_index);
2449 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
2450 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
2451 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
2452 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
2453 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
2454 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
2455 : : attr->virtio_version_1_0);
2456 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
2457 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
2458 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
2459 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
2460 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
2461 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
2462 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
2463 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
2464 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
2465 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
2466 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
2467 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
2468 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
2469 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
2470 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
2471 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
2472 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
2473 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
2474 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, pd, attr->pd);
2475 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
2476 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
2477 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
2478 [ # # ]: 0 : MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
2479 : 0 : virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2480 : : sizeof(out));
2481 [ # # ]: 0 : if (!virtq_obj->obj) {
2482 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0);
2483 : 0 : mlx5_free(virtq_obj);
2484 : 0 : return NULL;
2485 : : }
2486 [ # # ]: 0 : virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2487 : 0 : return virtq_obj;
2488 : : }
2489 : :
2490 : : /**
2491 : : * Modify VIRTQ using DevX API.
2492 : : *
2493 : : * @param[in] virtq_obj
2494 : : * Pointer to virtq object structure.
2495 : : * @param [in] attr
2496 : : * Pointer to modify virtq attributes structure.
2497 : : *
2498 : : * @return
2499 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2500 : : */
2501 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_virtq)
2502 : : int
2503 : 0 : mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
2504 : : struct mlx5_devx_virtq_attr *attr)
2505 : : {
2506 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
2507 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2508 : : void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
2509 : : void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
2510 : : void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
2511 : : int ret;
2512 : :
2513 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2514 : : MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
2515 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2516 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2517 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2518 [ # # ]: 0 : MLX5_SET64(virtio_net_q, virtq, modify_field_select,
2519 : : attr->mod_fields_bitmap);
2520 : 0 : MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
2521 [ # # ]: 0 : if (!attr->mod_fields_bitmap) {
2522 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ for no type set.");
2523 : 0 : rte_errno = EINVAL;
2524 : 0 : return -rte_errno;
2525 : : }
2526 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE)
2527 : 0 : MLX5_SET16(virtio_net_q, virtq, state, attr->state);
2528 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2529 : : MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) {
2530 : 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
2531 : : attr->dirty_bitmap_mkey);
2532 [ # # ]: 0 : MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
2533 : : attr->dirty_bitmap_addr);
2534 : 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
2535 : : attr->dirty_bitmap_size);
2536 : : }
2537 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2538 : : MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE)
2539 [ # # ]: 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
2540 : : attr->dirty_bitmap_dump_enable);
2541 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) {
2542 : 0 : MLX5_SET(virtio_q, virtctx, queue_period_mode,
2543 : : attr->hw_latency_mode);
2544 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_us,
2545 : : attr->hw_max_latency_us);
2546 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_max_count,
2547 : : attr->hw_max_pending_comp);
2548 : : }
2549 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) {
2550 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
2551 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
2552 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, available_addr,
2553 : : attr->available_addr);
2554 : : }
2555 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX)
2556 : 0 : MLX5_SET16(virtio_net_q, virtq, hw_available_index,
2557 : : attr->hw_available_index);
2558 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX)
2559 : 0 : MLX5_SET16(virtio_net_q, virtq, hw_used_index,
2560 : : attr->hw_used_index);
2561 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE)
2562 : 0 : MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type);
2563 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0)
2564 : 0 : MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
2565 : : attr->virtio_version_1_0);
2566 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY)
2567 : 0 : MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
2568 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2569 : : MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) {
2570 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
2571 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
2572 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
2573 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
2574 : : }
2575 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) {
2576 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
2577 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
2578 : : }
2579 : 0 : ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
2580 : : out, sizeof(out));
2581 [ # # ]: 0 : if (ret) {
2582 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2583 : 0 : rte_errno = errno;
2584 : 0 : return -rte_errno;
2585 : : }
2586 : : return ret;
2587 : : }
2588 : :
2589 : : /**
2590 : : * Query VIRTQ using DevX API.
2591 : : *
2592 : : * @param[in] virtq_obj
2593 : : * Pointer to virtq object structure.
2594 : : * @param [in/out] attr
2595 : : * Pointer to virtq attributes structure.
2596 : : *
2597 : : * @return
2598 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2599 : : */
2600 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_virtq)
2601 : : int
2602 : 0 : mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
2603 : : struct mlx5_devx_virtq_attr *attr)
2604 : : {
2605 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2606 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
2607 : : void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
2608 : : void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
2609 : : int ret;
2610 : :
2611 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2612 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2613 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2614 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2615 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2616 : 0 : ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
2617 : : out, sizeof(out));
2618 [ # # ]: 0 : if (ret) {
2619 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2620 : 0 : rte_errno = errno;
2621 : 0 : return -errno;
2622 : : }
2623 [ # # ]: 0 : attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
2624 : : hw_available_index);
2625 [ # # ]: 0 : attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
2626 [ # # ]: 0 : attr->state = MLX5_GET16(virtio_net_q, virtq, state);
2627 [ # # ]: 0 : attr->error_type = MLX5_GET16(virtio_net_q, virtq,
2628 : : virtio_q_context.error_type);
2629 : 0 : return ret;
2630 : : }
2631 : :
2632 : : /**
2633 : : * Create QP using DevX API.
2634 : : *
2635 : : * @param[in] ctx
2636 : : * Context returned from mlx5 open_device() glue function.
2637 : : * @param [in] attr
2638 : : * Pointer to QP attributes structure.
2639 : : *
2640 : : * @return
2641 : : * The DevX object created, NULL otherwise and rte_errno is set.
2642 : : */
2643 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_qp)
2644 : : struct mlx5_devx_obj *
2645 : 0 : mlx5_devx_cmd_create_qp(void *ctx,
2646 : : struct mlx5_devx_qp_attr *attr)
2647 : : {
2648 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
2649 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
2650 : 0 : struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
2651 : : sizeof(*qp_obj),
2652 : : 0, SOCKET_ID_ANY);
2653 : : void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2654 : :
2655 [ # # ]: 0 : if (!qp_obj) {
2656 : 0 : DRV_LOG(ERR, "Failed to allocate QP data.");
2657 : 0 : rte_errno = ENOMEM;
2658 : 0 : return NULL;
2659 : : }
2660 [ # # ]: 0 : MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
2661 [ # # ]: 0 : MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
2662 [ # # ]: 0 : MLX5_SET(qpc, qpc, pd, attr->pd);
2663 [ # # ]: 0 : MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
2664 [ # # ]: 0 : MLX5_SET(qpc, qpc, user_index, attr->user_index);
2665 [ # # ]: 0 : if (attr->uar_index) {
2666 [ # # ]: 0 : if (attr->mmo) {
2667 : : void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in,
2668 : : in, qpc_extension_and_pas_list);
2669 : : void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list,
2670 : : qpc_ext_and_pas_list, qpc_data_extension);
2671 : :
2672 [ # # ]: 0 : MLX5_SET(create_qp_in, in, qpc_ext, 1);
2673 [ # # ]: 0 : MLX5_SET(qpc_extension, qpc_ext, mmo, 1);
2674 : : }
2675 [ # # ]: 0 : MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2676 [ # # ]: 0 : MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
2677 [ # # ]: 0 : if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2678 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_page_size,
2679 : : attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2680 [ # # ]: 0 : if (attr->num_of_send_wqbbs) {
2681 : : MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs));
2682 [ # # ]: 0 : MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
2683 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_sq_size,
2684 : : rte_log2_u32(attr->num_of_send_wqbbs));
2685 : : } else {
2686 [ # # ]: 0 : MLX5_SET(qpc, qpc, no_sq, 1);
2687 : : }
2688 [ # # ]: 0 : if (attr->num_of_receive_wqes) {
2689 : : MLX5_ASSERT(RTE_IS_POWER_OF_2(
2690 : : attr->num_of_receive_wqes));
2691 [ # # ]: 0 : MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
2692 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
2693 : : MLX5_LOG_RQ_STRIDE_SHIFT);
2694 [ # # # # ]: 0 : MLX5_SET(qpc, qpc, log_rq_size,
2695 : : rte_log2_u32(attr->num_of_receive_wqes));
2696 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
2697 : : } else {
2698 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2699 : : }
2700 [ # # ]: 0 : if (attr->dbr_umem_valid) {
2701 [ # # ]: 0 : MLX5_SET(qpc, qpc, dbr_umem_valid,
2702 : : attr->dbr_umem_valid);
2703 [ # # ]: 0 : MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
2704 : : }
2705 [ # # ]: 0 : if (attr->cd_master)
2706 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_master, attr->cd_master);
2707 [ # # ]: 0 : if (attr->cd_slave_send)
2708 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_slave_send, attr->cd_slave_send);
2709 [ # # ]: 0 : if (attr->cd_slave_recv)
2710 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_slave_receive, attr->cd_slave_recv);
2711 [ # # ]: 0 : MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
2712 [ # # ]: 0 : MLX5_SET64(create_qp_in, in, wq_umem_offset,
2713 : : attr->wq_umem_offset);
2714 [ # # ]: 0 : MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
2715 [ # # ]: 0 : MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
2716 : : } else {
2717 : : /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
2718 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2719 [ # # ]: 0 : MLX5_SET(qpc, qpc, no_sq, 1);
2720 : : }
2721 : 0 : qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2722 : : sizeof(out));
2723 [ # # ]: 0 : if (!qp_obj->obj) {
2724 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0);
2725 : 0 : mlx5_free(qp_obj);
2726 : 0 : return NULL;
2727 : : }
2728 [ # # ]: 0 : qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
2729 : 0 : return qp_obj;
2730 : : }
2731 : :
2732 : : /**
2733 : : * Modify QP using DevX API.
2734 : : * Currently supports only force loop-back QP.
2735 : : *
2736 : : * @param[in] qp
2737 : : * Pointer to QP object structure.
2738 : : * @param [in] qp_st_mod_op
2739 : : * The QP state modification operation.
2740 : : * @param [in] remote_qp_id
2741 : : * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
2742 : : *
2743 : : * @return
2744 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2745 : : */
2746 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_qp_state)
2747 : : int
2748 : 0 : mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
2749 : : uint32_t remote_qp_id)
2750 : : {
2751 : : union {
2752 : : uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
2753 : : uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
2754 : : uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
2755 : : uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)];
2756 : : } in;
2757 : : union {
2758 : : uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
2759 : : uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
2760 : : uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
2761 : : uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)];
2762 : : } out;
2763 : : void *qpc;
2764 : : int ret;
2765 : : unsigned int inlen;
2766 : : unsigned int outlen;
2767 : :
2768 : : memset(&in, 0, sizeof(in));
2769 : : memset(&out, 0, sizeof(out));
2770 : 0 : MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
2771 [ # # # # : 0 : switch (qp_st_mod_op) {
# ]
2772 : 0 : case MLX5_CMD_OP_RST2INIT_QP:
2773 : 0 : MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
2774 : : qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
2775 : 0 : MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2776 : : MLX5_SET(qpc, qpc, rre, 1);
2777 [ # # ]: 0 : MLX5_SET(qpc, qpc, rwe, 1);
2778 : 0 : MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2779 : : inlen = sizeof(in.rst2init);
2780 : : outlen = sizeof(out.rst2init);
2781 : 0 : break;
2782 : 0 : case MLX5_CMD_OP_INIT2RTR_QP:
2783 : 0 : MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2784 : : qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2785 : 0 : MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2786 : 0 : MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2787 : : MLX5_SET(qpc, qpc, mtu, 1);
2788 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_msg_max, 30);
2789 : 0 : MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2790 : 0 : MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2791 : : inlen = sizeof(in.init2rtr);
2792 : : outlen = sizeof(out.init2rtr);
2793 : 0 : break;
2794 : 0 : case MLX5_CMD_OP_RTR2RTS_QP:
2795 : : qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2796 : 0 : MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2797 : 0 : MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16);
2798 : : MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2799 [ # # ]: 0 : MLX5_SET(qpc, qpc, retry_count, 7);
2800 [ # # ]: 0 : MLX5_SET(qpc, qpc, rnr_retry, 7);
2801 : : inlen = sizeof(in.rtr2rts);
2802 : : outlen = sizeof(out.rtr2rts);
2803 : 0 : break;
2804 : 0 : case MLX5_CMD_OP_QP_2RST:
2805 : 0 : MLX5_SET(2rst_qp_in, &in, qpn, qp->id);
2806 : : inlen = sizeof(in.qp2rst);
2807 : : outlen = sizeof(out.qp2rst);
2808 : 0 : break;
2809 : 0 : default:
2810 : 0 : DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2811 : : qp_st_mod_op);
2812 : 0 : rte_errno = EINVAL;
2813 : 0 : return -rte_errno;
2814 : : }
2815 : 0 : ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2816 [ # # ]: 0 : if (ret) {
2817 : 0 : DRV_LOG(ERR, "Failed to modify QP using DevX.");
2818 : 0 : rte_errno = errno;
2819 : 0 : return -rte_errno;
2820 : : }
2821 : : return ret;
2822 : : }
2823 : :
2824 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_virtio_q_counters)
2825 : : struct mlx5_devx_obj *
2826 : 0 : mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2827 : : {
2828 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2829 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2830 : 0 : struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2831 : : sizeof(*couners_obj), 0,
2832 : : SOCKET_ID_ANY);
2833 : : void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2834 : :
2835 [ # # ]: 0 : if (!couners_obj) {
2836 : 0 : DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2837 : 0 : rte_errno = ENOMEM;
2838 : 0 : return NULL;
2839 : : }
2840 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2841 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2842 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2843 : : MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2844 : 0 : couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2845 : : sizeof(out));
2846 [ # # ]: 0 : if (!couners_obj->obj) {
2847 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL,
2848 : : 0);
2849 : 0 : mlx5_free(couners_obj);
2850 : 0 : return NULL;
2851 : : }
2852 [ # # ]: 0 : couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2853 : 0 : return couners_obj;
2854 : : }
2855 : :
2856 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_virtio_q_counters)
2857 : : int
2858 : 0 : mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2859 : : struct mlx5_devx_virtio_q_couners_attr *attr)
2860 : : {
2861 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2862 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2863 : : void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2864 : : void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2865 : : virtio_q_counters);
2866 : : int ret;
2867 : :
2868 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2869 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2870 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2871 : : MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2872 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2873 : 0 : ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2874 : : sizeof(out));
2875 [ # # ]: 0 : if (ret) {
2876 : 0 : DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2877 : 0 : rte_errno = errno;
2878 : 0 : return -errno;
2879 : : }
2880 [ # # ]: 0 : attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2881 : : received_desc);
2882 [ # # ]: 0 : attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2883 : : completed_desc);
2884 [ # # ]: 0 : attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2885 : : error_cqes);
2886 [ # # ]: 0 : attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2887 : : bad_desc_errors);
2888 [ # # ]: 0 : attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2889 : : exceed_max_chain);
2890 [ # # ]: 0 : attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2891 : : invalid_buffer);
2892 : 0 : return ret;
2893 : : }
2894 : :
2895 : : /**
2896 : : * Create general object of type FLOW_HIT_ASO using DevX API.
2897 : : *
2898 : : * @param[in] ctx
2899 : : * Context returned from mlx5 open_device() glue function.
2900 : : * @param [in] pd
2901 : : * PD value to associate the FLOW_HIT_ASO object with.
2902 : : *
2903 : : * @return
2904 : : * The DevX object created, NULL otherwise and rte_errno is set.
2905 : : */
2906 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_flow_hit_aso_obj)
2907 : : struct mlx5_devx_obj *
2908 : 0 : mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2909 : : {
2910 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2911 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2912 : : struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2913 : : void *ptr = NULL;
2914 : :
2915 : 0 : flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2916 : : 0, SOCKET_ID_ANY);
2917 [ # # ]: 0 : if (!flow_hit_aso_obj) {
2918 : 0 : DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2919 : 0 : rte_errno = ENOMEM;
2920 : 0 : return NULL;
2921 : : }
2922 : : ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2923 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2924 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2925 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2926 : : MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2927 : : ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2928 [ # # ]: 0 : MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2929 : 0 : flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2930 : : out, sizeof(out));
2931 [ # # ]: 0 : if (!flow_hit_aso_obj->obj) {
2932 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0);
2933 : 0 : mlx5_free(flow_hit_aso_obj);
2934 : 0 : return NULL;
2935 : : }
2936 [ # # ]: 0 : flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2937 : 0 : return flow_hit_aso_obj;
2938 : : }
2939 : :
2940 : : /*
2941 : : * Create PD using DevX API.
2942 : : *
2943 : : * @param[in] ctx
2944 : : * Context returned from mlx5 open_device() glue function.
2945 : : *
2946 : : * @return
2947 : : * The DevX object created, NULL otherwise and rte_errno is set.
2948 : : */
2949 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_alloc_pd)
2950 : : struct mlx5_devx_obj *
2951 : 0 : mlx5_devx_cmd_alloc_pd(void *ctx)
2952 : : {
2953 : : struct mlx5_devx_obj *ppd =
2954 : 0 : mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2955 : 0 : u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2956 : 0 : u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2957 : :
2958 [ # # ]: 0 : if (!ppd) {
2959 : 0 : DRV_LOG(ERR, "Failed to allocate PD data.");
2960 : 0 : rte_errno = ENOMEM;
2961 : 0 : return NULL;
2962 : : }
2963 : 0 : MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2964 : 0 : ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2965 : : out, sizeof(out));
2966 [ # # ]: 0 : if (!ppd->obj) {
2967 : 0 : mlx5_free(ppd);
2968 : 0 : DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2969 : 0 : rte_errno = errno;
2970 : 0 : return NULL;
2971 : : }
2972 [ # # ]: 0 : ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2973 : 0 : return ppd;
2974 : : }
2975 : :
2976 : : /**
2977 : : * Create general object of type FLOW_METER_ASO using DevX API.
2978 : : *
2979 : : * @param[in] ctx
2980 : : * Context returned from mlx5 open_device() glue function.
2981 : : * @param [in] pd
2982 : : * PD value to associate the FLOW_METER_ASO object with.
2983 : : * @param [in] log_obj_size
2984 : : * log_obj_size define to allocate number of 2 * meters
2985 : : * in one FLOW_METER_ASO object.
2986 : : *
2987 : : * @return
2988 : : * The DevX object created, NULL otherwise and rte_errno is set.
2989 : : */
2990 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_flow_meter_aso_obj)
2991 : : struct mlx5_devx_obj *
2992 : 0 : mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
2993 : : uint32_t log_obj_size)
2994 : : {
2995 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
2996 : : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2997 : : struct mlx5_devx_obj *flow_meter_aso_obj;
2998 : : void *ptr;
2999 : :
3000 : 0 : flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
3001 : : sizeof(*flow_meter_aso_obj),
3002 : : 0, SOCKET_ID_ANY);
3003 [ # # ]: 0 : if (!flow_meter_aso_obj) {
3004 : 0 : DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
3005 : 0 : rte_errno = ENOMEM;
3006 : 0 : return NULL;
3007 : : }
3008 : : ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
3009 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3010 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3011 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3012 : : MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
3013 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
3014 : : log_obj_size);
3015 : : ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
3016 [ # # ]: 0 : MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
3017 : 0 : flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
3018 : : ctx, in, sizeof(in),
3019 : : out, sizeof(out));
3020 [ # # ]: 0 : if (!flow_meter_aso_obj->obj) {
3021 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0);
3022 : 0 : mlx5_free(flow_meter_aso_obj);
3023 : 0 : return NULL;
3024 : : }
3025 [ # # ]: 0 : flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
3026 : : out, obj_id);
3027 : 0 : return flow_meter_aso_obj;
3028 : : }
3029 : :
3030 : : /*
3031 : : * Create general object of type CONN_TRACK_OFFLOAD using DevX API.
3032 : : *
3033 : : * @param[in] ctx
3034 : : * Context returned from mlx5 open_device() glue function.
3035 : : * @param [in] pd
3036 : : * PD value to associate the CONN_TRACK_OFFLOAD ASO object with.
3037 : : * @param [in] log_obj_size
3038 : : * log_obj_size to allocate its power of 2 * objects
3039 : : * in one CONN_TRACK_OFFLOAD bulk allocation.
3040 : : *
3041 : : * @return
3042 : : * The DevX object created, NULL otherwise and rte_errno is set.
3043 : : */
3044 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_conn_track_offload_obj)
3045 : : struct mlx5_devx_obj *
3046 : 0 : mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd,
3047 : : uint32_t log_obj_size)
3048 : : {
3049 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0};
3050 : : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
3051 : : struct mlx5_devx_obj *ct_aso_obj;
3052 : : void *ptr;
3053 : :
3054 : 0 : ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj),
3055 : : 0, SOCKET_ID_ANY);
3056 [ # # ]: 0 : if (!ct_aso_obj) {
3057 : 0 : DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object.");
3058 : 0 : rte_errno = ENOMEM;
3059 : 0 : return NULL;
3060 : : }
3061 : : ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr);
3062 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3063 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3064 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3065 : : MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD);
3066 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size);
3067 : : ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload);
3068 [ # # ]: 0 : MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd);
3069 : 0 : ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3070 : : out, sizeof(out));
3071 [ # # ]: 0 : if (!ct_aso_obj->obj) {
3072 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0);
3073 : 0 : mlx5_free(ct_aso_obj);
3074 : 0 : return NULL;
3075 : : }
3076 [ # # ]: 0 : ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3077 : 0 : return ct_aso_obj;
3078 : : }
3079 : :
3080 : : /**
3081 : : * Create general object of type GENEVE TLV option using DevX API.
3082 : : *
3083 : : * @param[in] ctx
3084 : : * Context returned from mlx5 open_device() glue function.
3085 : : * @param[in] attr
3086 : : * Pointer to GENEVE TLV option attributes structure.
3087 : : *
3088 : : * @return
3089 : : * The DevX object created, NULL otherwise and rte_errno is set.
3090 : : */
3091 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_geneve_tlv_option)
3092 : : struct mlx5_devx_obj *
3093 : 0 : mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
3094 : : struct mlx5_devx_geneve_tlv_option_attr *attr)
3095 : : {
3096 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
3097 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3098 : 0 : struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
3099 : : sizeof(*geneve_tlv_opt_obj),
3100 : : 0, SOCKET_ID_ANY);
3101 : :
3102 [ # # ]: 0 : if (!geneve_tlv_opt_obj) {
3103 : 0 : DRV_LOG(ERR, "Failed to allocate GENEVE TLV option object.");
3104 : 0 : rte_errno = ENOMEM;
3105 : 0 : return NULL;
3106 : : }
3107 : : void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
3108 : : void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
3109 : : geneve_tlv_opt);
3110 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
3111 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3112 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
3113 : : MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
3114 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_type, attr->option_type);
3115 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_data_length,
3116 : : attr->option_data_len);
3117 [ # # ]: 0 : if (attr->option_class_ignore)
3118 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_class_ignore,
3119 : : attr->option_class_ignore);
3120 : : else
3121 [ # # # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_class,
3122 : : rte_be_to_cpu_16(attr->option_class));
3123 [ # # ]: 0 : if (attr->offset_valid) {
3124 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, sample_offset_valid,
3125 : : attr->offset_valid);
3126 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, sample_offset,
3127 : : attr->sample_offset);
3128 : : }
3129 : 0 : geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
3130 : : sizeof(in), out,
3131 : : sizeof(out));
3132 [ # # ]: 0 : if (!geneve_tlv_opt_obj->obj) {
3133 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create GENEVE TLV option", NULL, 0);
3134 : 0 : mlx5_free(geneve_tlv_opt_obj);
3135 : 0 : return NULL;
3136 : : }
3137 [ # # ]: 0 : geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3138 : 0 : return geneve_tlv_opt_obj;
3139 : : }
3140 : :
3141 : : /**
3142 : : * Query GENEVE TLV option using DevX API.
3143 : : *
3144 : : * @param[in] ctx
3145 : : * Context used to create GENEVE TLV option object.
3146 : : * @param[in] geneve_tlv_opt_obj
3147 : : * DevX object of the GENEVE TLV option.
3148 : : * @param[out] attr
3149 : : * Pointer to match sample info attributes structure.
3150 : : *
3151 : : * @return
3152 : : * 0 on success, a negative errno otherwise and rte_errno is set.
3153 : : */
3154 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_geneve_tlv_option)
3155 : : int
3156 : 0 : mlx5_devx_cmd_query_geneve_tlv_option(void *ctx,
3157 : : struct mlx5_devx_obj *geneve_tlv_opt_obj,
3158 : : struct mlx5_devx_match_sample_info_query_attr *attr)
3159 : : {
3160 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
3161 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_geneve_tlv_option_out)] = {0};
3162 : : void *hdr = MLX5_ADDR_OF(query_geneve_tlv_option_out, in, hdr);
3163 : : void *opt = MLX5_ADDR_OF(query_geneve_tlv_option_out, out,
3164 : : geneve_tlv_opt);
3165 : : int ret;
3166 : :
3167 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
3168 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
3169 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
3170 : : MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
3171 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, geneve_tlv_opt_obj->id);
3172 : : /* Call first query to get sample handle. */
3173 : 0 : ret = mlx5_glue->devx_obj_query(geneve_tlv_opt_obj->obj, in, sizeof(in),
3174 : : out, sizeof(out));
3175 [ # # ]: 0 : if (ret) {
3176 : 0 : DRV_LOG(ERR, "Failed to query GENEVE TLV option using DevX.");
3177 : 0 : rte_errno = errno;
3178 : 0 : return -errno;
3179 : : }
3180 : : /* Call second query to get sample information. */
3181 [ # # # # ]: 0 : if (MLX5_GET(geneve_tlv_option, opt, sample_id_valid)) {
3182 [ # # ]: 0 : uint32_t sample_id = MLX5_GET(geneve_tlv_option, opt,
3183 : : geneve_sample_field_id);
3184 : :
3185 : 0 : return mlx5_devx_cmd_match_sample_info_query(ctx, sample_id,
3186 : : attr);
3187 : : }
3188 : 0 : DRV_LOG(DEBUG, "GENEVE TLV option sample isn't valid.");
3189 : 0 : return 0;
3190 : : }
3191 : :
3192 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_wq_query)
3193 : : int
3194 : 0 : mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
3195 : : {
3196 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3197 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
3198 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
3199 : : int rc;
3200 : : void *rq_ctx;
3201 : :
3202 : 0 : MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
3203 : 0 : MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
3204 : 0 : rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
3205 [ # # ]: 0 : if (rc) {
3206 : 0 : rte_errno = errno;
3207 : 0 : DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
3208 : : "rc = %d, errno = %d.", rc, errno);
3209 : 0 : return -rc;
3210 : : };
3211 : : rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
3212 [ # # ]: 0 : *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
3213 : 0 : return 0;
3214 : : #else
3215 : : (void)wq;
3216 : : (void)counter_set_id;
3217 : : return -ENOTSUP;
3218 : : #endif
3219 : : }
3220 : :
3221 : : /*
3222 : : * Allocate queue counters via devx interface.
3223 : : *
3224 : : * @param[in] ctx
3225 : : * Context returned from mlx5 open_device() glue function.
3226 : : * @param[out] syndrome
3227 : : * Get syndrome of devx command response.
3228 : : *
3229 : : * @return
3230 : : * Pointer to counter object on success, a NULL value otherwise and
3231 : : * rte_errno is set.
3232 : : */
3233 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_queue_counter_alloc)
3234 : : struct mlx5_devx_obj *
3235 : 0 : mlx5_devx_cmd_queue_counter_alloc(void *ctx, int *syndrome)
3236 : : {
3237 : : int status;
3238 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
3239 : : SOCKET_ID_ANY);
3240 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0};
3241 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
3242 : :
3243 [ # # ]: 0 : if (!dcs) {
3244 : 0 : rte_errno = ENOMEM;
3245 : 0 : return NULL;
3246 : : }
3247 : 0 : MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
3248 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
3249 : : sizeof(out));
3250 [ # # ]: 0 : if (!dcs->obj) {
3251 [ # # # # ]: 0 : DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0);
3252 [ # # ]: 0 : status = MLX5_GET(alloc_q_counter_out, out, status);
3253 [ # # ]: 0 : if (status && syndrome)
3254 [ # # ]: 0 : *syndrome = MLX5_GET(alloc_q_counter_out, out, syndrome);
3255 : 0 : mlx5_free(dcs);
3256 : 0 : return NULL;
3257 : : }
3258 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
3259 : 0 : return dcs;
3260 : : }
3261 : :
3262 : : /**
3263 : : * Query queue counters values.
3264 : : *
3265 : : * @param[in] dcs
3266 : : * devx object of the queue counter set.
3267 : : * @param[in] clear
3268 : : * Whether hardware should clear the counters after the query or not.
3269 : : * @param[out] out_of_buffers
3270 : : * Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
3271 : : *
3272 : : * @return
3273 : : * 0 on success, a negative value otherwise.
3274 : : */
3275 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_queue_counter_query)
3276 : : int
3277 : 0 : mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
3278 : : uint32_t *out_of_buffers)
3279 : : {
3280 : 0 : uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
3281 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
3282 : : int rc;
3283 : :
3284 : 0 : MLX5_SET(query_q_counter_in, in, opcode,
3285 : : MLX5_CMD_OP_QUERY_Q_COUNTER);
3286 : 0 : MLX5_SET(query_q_counter_in, in, op_mod, 0);
3287 : 0 : MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
3288 : 0 : MLX5_SET(query_q_counter_in, in, clear, !!clear);
3289 : 0 : rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
3290 : : sizeof(out));
3291 [ # # ]: 0 : if (rc) {
3292 : 0 : DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
3293 : 0 : rte_errno = rc;
3294 : 0 : return -rc;
3295 : : }
3296 [ # # ]: 0 : *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
3297 : 0 : return 0;
3298 : : }
3299 : :
3300 : : /**
3301 : : * Create general object of type DEK using DevX API.
3302 : : *
3303 : : * @param[in] ctx
3304 : : * Context returned from mlx5 open_device() glue function.
3305 : : * @param [in] attr
3306 : : * Pointer to DEK attributes structure.
3307 : : *
3308 : : * @return
3309 : : * The DevX object created, NULL otherwise and rte_errno is set.
3310 : : */
3311 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_dek_obj)
3312 : : struct mlx5_devx_obj *
3313 : 0 : mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)
3314 : : {
3315 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};
3316 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3317 : : struct mlx5_devx_obj *dek_obj = NULL;
3318 : : void *ptr = NULL, *key_addr = NULL;
3319 : :
3320 : 0 : dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),
3321 : : 0, SOCKET_ID_ANY);
3322 [ # # ]: 0 : if (dek_obj == NULL) {
3323 : 0 : DRV_LOG(ERR, "Failed to allocate DEK object data");
3324 : 0 : rte_errno = ENOMEM;
3325 : 0 : return NULL;
3326 : : }
3327 : : ptr = MLX5_ADDR_OF(create_dek_in, in, hdr);
3328 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3329 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3330 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3331 : : MLX5_GENERAL_OBJ_TYPE_DEK);
3332 : : ptr = MLX5_ADDR_OF(create_dek_in, in, dek);
3333 [ # # ]: 0 : MLX5_SET(dek, ptr, key_size, attr->key_size);
3334 [ # # ]: 0 : MLX5_SET(dek, ptr, has_keytag, attr->has_keytag);
3335 [ # # ]: 0 : MLX5_SET(dek, ptr, key_purpose, attr->key_purpose);
3336 [ # # ]: 0 : MLX5_SET(dek, ptr, pd, attr->pd);
3337 [ # # ]: 0 : MLX5_SET64(dek, ptr, opaque, attr->opaque);
3338 : : key_addr = MLX5_ADDR_OF(dek, ptr, key);
3339 : 0 : memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
3340 : 0 : dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3341 : : out, sizeof(out));
3342 [ # # ]: 0 : if (dek_obj->obj == NULL) {
3343 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0);
3344 : 0 : mlx5_free(dek_obj);
3345 : 0 : return NULL;
3346 : : }
3347 [ # # ]: 0 : dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3348 : 0 : return dek_obj;
3349 : : }
3350 : :
3351 : : /**
3352 : : * Create general object of type IMPORT_KEK using DevX API.
3353 : : *
3354 : : * @param[in] ctx
3355 : : * Context returned from mlx5 open_device() glue function.
3356 : : * @param [in] attr
3357 : : * Pointer to IMPORT_KEK attributes structure.
3358 : : *
3359 : : * @return
3360 : : * The DevX object created, NULL otherwise and rte_errno is set.
3361 : : */
3362 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_import_kek_obj)
3363 : : struct mlx5_devx_obj *
3364 : 0 : mlx5_devx_cmd_create_import_kek_obj(void *ctx,
3365 : : struct mlx5_devx_import_kek_attr *attr)
3366 : : {
3367 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0};
3368 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3369 : : struct mlx5_devx_obj *import_kek_obj = NULL;
3370 : : void *ptr = NULL, *key_addr = NULL;
3371 : :
3372 : 0 : import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj),
3373 : : 0, SOCKET_ID_ANY);
3374 [ # # ]: 0 : if (import_kek_obj == NULL) {
3375 : 0 : DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data");
3376 : 0 : rte_errno = ENOMEM;
3377 : 0 : return NULL;
3378 : : }
3379 : : ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr);
3380 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3381 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3382 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3383 : : MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK);
3384 : : ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek);
3385 [ # # ]: 0 : MLX5_SET(import_kek, ptr, key_size, attr->key_size);
3386 : : key_addr = MLX5_ADDR_OF(import_kek, ptr, key);
3387 : 0 : memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
3388 : 0 : import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3389 : : out, sizeof(out));
3390 [ # # ]: 0 : if (import_kek_obj->obj == NULL) {
3391 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0);
3392 : 0 : mlx5_free(import_kek_obj);
3393 : 0 : return NULL;
3394 : : }
3395 [ # # ]: 0 : import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3396 : 0 : return import_kek_obj;
3397 : : }
3398 : :
3399 : : /**
3400 : : * Create general object of type CREDENTIAL using DevX API.
3401 : : *
3402 : : * @param[in] ctx
3403 : : * Context returned from mlx5 open_device() glue function.
3404 : : * @param [in] attr
3405 : : * Pointer to CREDENTIAL attributes structure.
3406 : : *
3407 : : * @return
3408 : : * The DevX object created, NULL otherwise and rte_errno is set.
3409 : : */
3410 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_credential_obj)
3411 : : struct mlx5_devx_obj *
3412 : 0 : mlx5_devx_cmd_create_credential_obj(void *ctx,
3413 : : struct mlx5_devx_credential_attr *attr)
3414 : : {
3415 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0};
3416 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3417 : : struct mlx5_devx_obj *credential_obj = NULL;
3418 : : void *ptr = NULL, *credential_addr = NULL;
3419 : :
3420 : 0 : credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj),
3421 : : 0, SOCKET_ID_ANY);
3422 [ # # ]: 0 : if (credential_obj == NULL) {
3423 : 0 : DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data");
3424 : 0 : rte_errno = ENOMEM;
3425 : 0 : return NULL;
3426 : : }
3427 : : ptr = MLX5_ADDR_OF(create_credential_in, in, hdr);
3428 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3429 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3430 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3431 : : MLX5_GENERAL_OBJ_TYPE_CREDENTIAL);
3432 : : ptr = MLX5_ADDR_OF(create_credential_in, in, credential);
3433 [ # # ]: 0 : MLX5_SET(credential, ptr, credential_role, attr->credential_role);
3434 : : credential_addr = MLX5_ADDR_OF(credential, ptr, credential);
3435 : 0 : memcpy(credential_addr, (void *)(attr->credential),
3436 : : MLX5_CRYPTO_CREDENTIAL_SIZE);
3437 : 0 : credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3438 : : out, sizeof(out));
3439 [ # # ]: 0 : if (credential_obj->obj == NULL) {
3440 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0);
3441 : 0 : mlx5_free(credential_obj);
3442 : 0 : return NULL;
3443 : : }
3444 [ # # ]: 0 : credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3445 : 0 : return credential_obj;
3446 : : }
3447 : :
3448 : : /**
3449 : : * Create general object of type CRYPTO_LOGIN using DevX API.
3450 : : *
3451 : : * @param[in] ctx
3452 : : * Context returned from mlx5 open_device() glue function.
3453 : : * @param [in] attr
3454 : : * Pointer to CRYPTO_LOGIN attributes structure.
3455 : : *
3456 : : * @return
3457 : : * The DevX object created, NULL otherwise and rte_errno is set.
3458 : : */
3459 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_crypto_login_obj)
3460 : : struct mlx5_devx_obj *
3461 : 0 : mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
3462 : : struct mlx5_devx_crypto_login_attr *attr)
3463 : : {
3464 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0};
3465 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3466 : : struct mlx5_devx_obj *crypto_login_obj = NULL;
3467 : : void *ptr = NULL, *credential_addr = NULL;
3468 : :
3469 : 0 : crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj),
3470 : : 0, SOCKET_ID_ANY);
3471 [ # # ]: 0 : if (crypto_login_obj == NULL) {
3472 : 0 : DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data");
3473 : 0 : rte_errno = ENOMEM;
3474 : 0 : return NULL;
3475 : : }
3476 : : ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr);
3477 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3478 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3479 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3480 : : MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN);
3481 : : ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login);
3482 [ # # ]: 0 : MLX5_SET(crypto_login, ptr, credential_pointer,
3483 : : attr->credential_pointer);
3484 [ # # ]: 0 : MLX5_SET(crypto_login, ptr, session_import_kek_ptr,
3485 : : attr->session_import_kek_ptr);
3486 : : credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential);
3487 : 0 : memcpy(credential_addr, (void *)(attr->credential),
3488 : : MLX5_CRYPTO_CREDENTIAL_SIZE);
3489 : 0 : crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3490 : : out, sizeof(out));
3491 [ # # ]: 0 : if (crypto_login_obj->obj == NULL) {
3492 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0);
3493 : 0 : mlx5_free(crypto_login_obj);
3494 : 0 : return NULL;
3495 : : }
3496 [ # # ]: 0 : crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3497 : 0 : return crypto_login_obj;
3498 : : }
3499 : :
3500 : : /**
3501 : : * Query LAG context.
3502 : : *
3503 : : * @param[in] ctx
3504 : : * Pointer to ibv_context, returned from mlx5dv_open_device.
3505 : : * @param[out] lag_ctx
3506 : : * Pointer to struct mlx5_devx_lag_context, to be set by the routine.
3507 : : *
3508 : : * @return
3509 : : * 0 on success, a negative value otherwise.
3510 : : */
3511 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_lag)
3512 : : int
3513 : 0 : mlx5_devx_cmd_query_lag(void *ctx,
3514 : : struct mlx5_devx_lag_context *lag_ctx)
3515 : : {
3516 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0};
3517 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0};
3518 : : void *lctx;
3519 : : int rc;
3520 : :
3521 : 0 : MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG);
3522 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
3523 [ # # ]: 0 : if (rc)
3524 : 0 : goto error;
3525 : : lctx = MLX5_ADDR_OF(query_lag_out, out, context);
3526 [ # # ]: 0 : lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx,
3527 : : fdb_selection_mode);
3528 [ # # ]: 0 : lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx,
3529 : : port_select_mode);
3530 [ # # ]: 0 : lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state);
3531 [ # # ]: 0 : lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx,
3532 : : tx_remap_affinity_2);
3533 [ # # ]: 0 : lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx,
3534 : : tx_remap_affinity_1);
3535 : 0 : return 0;
3536 : : error:
3537 : 0 : rc = (rc > 0) ? -rc : rc;
3538 : 0 : return rc;
3539 : : }
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